📄 ledshow.vhd
字号:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ledshow is
Port ( clk : in std_logic;
reset : in std_logic;
xdot : in std_logic_vector(8 downto 0);
ydot : in std_logic_vector(8 downto 0);
ledA1 : out std_logic;
ledA2 : out std_logic;
ledA3 : out std_logic;
ledA4 : out std_logic;
leddata : out std_logic_vector(6 downto 0));
end ledshow;
architecture Behavioral of ledshow is
component segdecode
Port ( datain : in std_logic_vector(3 downto 0);
dataout : out std_logic_vector(6 downto 0)
);
end component;
signal sel : std_logic_vector(1 downto 0);
signal data : std_logic_vector(3 downto 0);
signal dataout : std_logic_vector(6 downto 0);
begin
selcount: process (reset,clk)
begin
if (reset='0') then
sel <= "00";
elsif (clk'event and clk='1') then
sel <= sel+'1';
end if;
end process;
selchoice: process (sel,xdot,ydot)
begin
ledA1 <= '0';
ledA2 <= '0';
ledA3 <= '0';
ledA4 <= '0';
case sel is
when "00" =>
ledA1 <= '1';
data <= xdot(3 downto 0);
when "01" =>
ledA2 <= '1';
data <= xdot(7 downto 4);
when "10" =>
ledA3 <= '1';
data <= ydot(3 downto 0);
when "11" =>
ledA4 <= '1';
data <= ydot(7 downto 4);
when others => data <= "0000";
end case;
end process;
decode: segdecode Port map(
datain => data,
dataout => dataout
);
leddata <= dataout;
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -