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用vhdl实现ps2鼠标的源程序

Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/digitalsword/examples/ps2mouse/segdecode.vhd in Library work.
Entity <segdecode> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/digitalsword/examples/ps2mouse/ledshow.vhd in Library work.
Entity <ledshow> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ledshow> (Architecture <Behavioral>).
INFO:Xst:1561 - E:/digitalsword/examples/ps2mouse/ledshow.vhd line 58: Mux is complete : default of case is discarded
Entity <ledshow> analyzed. Unit <ledshow> generated.

Analyzing Entity <segdecode> (Architecture <behavioral>).
INFO:Xst:1561 - E:/digitalsword/examples/ps2mouse/segdecode.vhd line 32: Mux is complete : default of case is discarded
Entity <segdecode> analyzed. Unit <segdecode> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <segdecode>.
    Related source file is E:/digitalsword/examples/ps2mouse/segdecode.vhd.
    Found 16x7-bit ROM for signal <hex>.
    Summary:
	inferred   1 ROM(s).
Unit <segdecode> synthesized.


Synthesizing Unit <ledshow>.
    Related source file is E:/digitalsword/examples/ps2mouse/ledshow.vhd.
WARNING:Xst:647 - Input <xdot<8>> is never used.
WARNING:Xst:647 - Input <ydot<8>> is never used.
    Found 4-bit 4-to-1 multiplexer for signal <data>.
    Found 2-bit up counter for signal <sel>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 Multiplexer(s).
Unit <ledshow> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x7-bit ROM                     : 1
# Counters                         : 1
  2-bit up counter                 : 1
# Multiplexers                     : 1
  4-bit 4-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ledshow> ...
Loading device for application Xst from file 'v100.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ledshow, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100tq144-5 

 Number of Slices:                      12  out of   1200     1%  
 Number of Slice Flip Flops:             2  out of   2400     0%  
 Number of 4 input LUTs:                22  out of   2400     0%  
 Number of bonded IOBs:                 28  out of     96    29%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 5.198ns (Maximum Frequency: 192.382MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.130ns
   Maximum combinational path delay: 12.412ns

=========================================================================
Completed process "Synthesize".