ledshow.syr

用vhdl实现ps2鼠标的源程序

Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: ledshow.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ledshow.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : ledshow
Output Format                      : NGC
Target Device                      : xc2s100-5-tq144

---- Source Options
Top Module Name                    : ledshow
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ledshow.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/digitalsword/examples/ps2mouse/segdecode.vhd in Library work.
Entity <segdecode> (Architecture <Behavioral>) compiled.
Compiling vhdl file E:/digitalsword/examples/ps2mouse/ledshow.vhd in Library work.
Entity <ledshow> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ledshow> (Architecture <Behavioral>).
INFO:Xst:1561 - E:/digitalsword/examples/ps2mouse/ledshow.vhd line 58: Mux is complete : default of case is discarded
Entity <ledshow> analyzed. Unit <ledshow> generated.

Analyzing Entity <segdecode> (Architecture <behavioral>).
INFO:Xst:1561 - E:/digitalsword/examples/ps2mouse/segdecode.vhd line 32: Mux is complete : default of case is discarded
Entity <segdecode> analyzed. Unit <segdecode> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <segdecode>.
    Related source file is E:/digitalsword/examples/ps2mouse/segdecode.vhd.
    Found 16x7-bit ROM for signal <hex>.
    Summary:
	inferred   1 ROM(s).
Unit <segdecode> synthesized.


Synthesizing Unit <ledshow>.
    Related source file is E:/digitalsword/examples/ps2mouse/ledshow.vhd.
WARNING:Xst:647 - Input <xdot<8>> is never used.
WARNING:Xst:647 - Input <ydot<8>> is never used.
    Found 4-bit 4-to-1 multiplexer for signal <data>.
    Found 2-bit up counter for signal <sel>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 Multiplexer(s).
Unit <ledshow> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x7-bit ROM                     : 1
# Counters                         : 1
  2-bit up counter                 : 1
# Multiplexers                     : 1
  4-bit 4-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ledshow> ...
Loading device for application Xst from file 'v100.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ledshow, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ledshow.ngr
Top Level Output File Name         : ledshow
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 31

Macro Statistics :
# ROMs                             : 1
#      16x7-bit ROM                : 1
# Registers                        : 1
#      2-bit register              : 1
# Multiplexers                     : 1
#      4-bit 4-to-1 multiplexer    : 1

Cell Usage :
# BELS                             : 26
#      LUT1                        : 1
#      LUT1_L                      : 1
#      LUT2                        : 4
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT4                        : 7
#      MUXF5                       : 4
# FlipFlops/Latches                : 2
#      FDC                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 28
#      IBUF                        : 17
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100tq144-5 

 Number of Slices:                      12  out of   1200     1%  
 Number of Slice Flip Flops:             2  out of   2400     0%  
 Number of 4 input LUTs:                22  out of   2400     0%  
 Number of bonded IOBs:                 28  out of     96    29%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 5.198ns (Maximum Frequency: 192.382MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.130ns
   Maximum combinational path delay: 12.412ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               5.198ns (Levels of Logic = 1)
  Source:            sel_1 (FF)
  Destination:       sel_1 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: sel_1 to sel_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.292   2.500  sel_1 (sel_1)
     LUT2_L:I1->LO         1   0.653   0.000  sel_Madd__n0000_Mxor_Result<1>_Result1 (sel__n0000<1>)
     FDC:D                     0.753          sel_1
    ----------------------------------------
    Total                      5.198ns (2.698ns logic, 2.500ns route)
                                       (51.9% logic, 48.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              14.130ns (Levels of Logic = 4)
  Source:            sel_1 (FF)
  Destination:       leddata<6> (PAD)
  Source Clock:      clk rising

  Data Path: sel_1 to leddata<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.292   2.500  sel_1 (sel_1)
     LUT3:I0->O            1   0.653   0.000  Mmux_data_inst_mux_f5_0111_F (N396)
     MUXF5:I0->O           7   0.375   1.950  Mmux_data_inst_mux_f5_0111 (data<0>)
     LUT4:I0->O            1   0.653   1.150  decode_Mrom_hex_inst_lut4_01 (leddata_0_OBUF)
     OBUF:I->O                 5.557          leddata_0_OBUF (leddata<0>)
    ----------------------------------------
    Total                     14.130ns (8.530ns logic, 5.600ns route)
                                       (60.4% logic, 39.6% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               12.412ns (Levels of Logic = 5)
  Source:            xdot<0> (PAD)
  Destination:       leddata<6> (PAD)

  Data Path: xdot<0> to leddata<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.924   1.150  xdot_0_IBUF (xdot_0_IBUF)
     LUT3:I1->O            1   0.653   0.000  Mmux_data_inst_mux_f5_0111_F (N396)
     MUXF5:I0->O           7   0.375   1.950  Mmux_data_inst_mux_f5_0111 (data<0>)
     LUT4:I0->O            1   0.653   1.150  decode_Mrom_hex_inst_lut4_01 (leddata_0_OBUF)
     OBUF:I->O                 5.557          leddata_0_OBUF (leddata<0>)
    ----------------------------------------
    Total                     12.412ns (8.162ns logic, 4.250ns route)
                                       (65.8% logic, 34.2% route)

=========================================================================
CPU : 3.70 / 5.81 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 53988 kilobytes