mouse_timesim.vhd

用vhdl实现ps2鼠标的源程序

      ADR2 => N244,
      ADR3 => VCC,
      O => N353
    );
  m2_state_FFD5_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m2_state_FFD5_SRMUX_OUTPUTNOT
    );
  m2_state_FFD6_59 : X_FF
    port map (
      I => N353,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD5_FFY_ASYNC_FF_GSR_OR,
      O => m2_state_FFD6
    );
  m2_state_FFD5_FFY_RSTOR : X_BUF
    port map (
      I => m2_state_FFD5_SRMUX_OUTPUTNOT,
      O => m2_state_FFD5_FFY_RST
    );
  m2_state_FFD5_FFY_ASYNC_FF_GSR_OR_60 : X_OR2
    port map (
      I0 => m2_state_FFD5_FFY_RST,
      I1 => GSR,
      O => m2_state_FFD5_FFY_ASYNC_FF_GSR_OR
    );
  m2_state_FFD5_61 : X_FF
    port map (
      I => m2_state_FFD4,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD5_FFX_ASYNC_FF_GSR_OR,
      O => m2_state_FFD5
    );
  m2_state_FFD5_FFX_RSTOR : X_BUF
    port map (
      I => m2_state_FFD5_SRMUX_OUTPUTNOT,
      O => m2_state_FFD5_FFX_RST
    );
  m2_state_FFD5_FFX_ASYNC_FF_GSR_OR_62 : X_OR2
    port map (
      I0 => m2_state_FFD5_FFX_RST,
      I1 => GSR,
      O => m2_state_FFD5_FFX_ASYNC_FF_GSR_OR
    );
  q_12_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_12_SRMUX_OUTPUTNOT
    );
  q_11 : X_FF
    port map (
      I => q(12),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_12_FFY_ASYNC_FF_GSR_OR,
      O => q(11)
    );
  q_12_FFY_RSTOR : X_BUF
    port map (
      I => q_12_SRMUX_OUTPUTNOT,
      O => q_12_FFY_RST
    );
  q_12_FFY_ASYNC_FF_GSR_OR_63 : X_OR2
    port map (
      I0 => q_12_FFY_RST,
      I1 => GSR,
      O => q_12_FFY_ASYNC_FF_GSR_OR
    );
  q_12 : X_FF
    port map (
      I => q(13),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_12_FFX_ASYNC_FF_GSR_OR,
      O => q(12)
    );
  q_12_FFX_RSTOR : X_BUF
    port map (
      I => q_12_SRMUX_OUTPUTNOT,
      O => q_12_FFX_RST
    );
  q_12_FFX_ASYNC_FF_GSR_OR_64 : X_OR2
    port map (
      I0 => q_12_FFX_RST,
      I1 => GSR,
      O => q_12_FFX_ASYNC_FF_GSR_OR
    );
  q_22_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_22_SRMUX_OUTPUTNOT
    );
  q_21 : X_FF
    port map (
      I => q(22),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_22_FFY_ASYNC_FF_GSR_OR,
      O => q(21)
    );
  q_22_FFY_RSTOR : X_BUF
    port map (
      I => q_22_SRMUX_OUTPUTNOT,
      O => q_22_FFY_RST
    );
  q_22_FFY_ASYNC_FF_GSR_OR_65 : X_OR2
    port map (
      I0 => q_22_FFY_RST,
      I1 => GSR,
      O => q_22_FFY_ASYNC_FF_GSR_OR
    );
  q_22 : X_FF
    port map (
      I => q(23),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_22_FFX_ASYNC_FF_GSR_OR,
      O => q(22)
    );
  q_22_FFX_RSTOR : X_BUF
    port map (
      I => q_22_SRMUX_OUTPUTNOT,
      O => q_22_FFX_RST
    );
  q_22_FFX_ASYNC_FF_GSR_OR_66 : X_OR2
    port map (
      I0 => q_22_FFX_RST,
      I1 => GSR,
      O => q_22_FFX_ASYNC_FF_GSR_OR
    );
  q_14_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_14_SRMUX_OUTPUTNOT
    );
  q_13 : X_FF
    port map (
      I => q(14),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_14_FFY_ASYNC_FF_GSR_OR,
      O => q(13)
    );
  q_14_FFY_RSTOR : X_BUF
    port map (
      I => q_14_SRMUX_OUTPUTNOT,
      O => q_14_FFY_RST
    );
  q_14_FFY_ASYNC_FF_GSR_OR_67 : X_OR2
    port map (
      I0 => q_14_FFY_RST,
      I1 => GSR,
      O => q_14_FFY_ASYNC_FF_GSR_OR
    );
  q_14 : X_FF
    port map (
      I => q(15),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_14_FFX_ASYNC_FF_GSR_OR,
      O => q(14)
    );
  q_14_FFX_RSTOR : X_BUF
    port map (
      I => q_14_SRMUX_OUTPUTNOT,
      O => q_14_FFX_RST
    );
  q_14_FFX_ASYNC_FF_GSR_OR_68 : X_OR2
    port map (
      I0 => q_14_FFX_RST,
      I1 => GSR,
      O => q_14_FFX_ASYNC_FF_GSR_OR
    );
  y_increment_0_OBUF_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => y_increment_0_OBUF_SRMUX_OUTPUTNOT
    );
  y_increment_0 : X_FF
    port map (
      I => q(23),
      CE => m2_state_FFD5,
      CLK => clk_BUFGP,
      SET => GND,
      RST => y_increment_0_OBUF_FFY_ASYNC_FF_GSR_OR,
      O => y_increment_0_OBUF
    );
  y_increment_0_OBUF_FFY_RSTOR : X_BUF
    port map (
      I => y_increment_0_OBUF_SRMUX_OUTPUTNOT,
      O => y_increment_0_OBUF_FFY_RST
    );
  y_increment_0_OBUF_FFY_ASYNC_FF_GSR_OR_69 : X_OR2
    port map (
      I0 => y_increment_0_OBUF_FFY_RST,
      I1 => GSR,
      O => y_increment_0_OBUF_FFY_ASYNC_FF_GSR_OR
    );
  q_31_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_31_SRMUX_OUTPUTNOT
    );
  q_31 : X_FF
    port map (
      I => q(32),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_31_FFY_ASYNC_FF_GSR_OR,
      O => q(31)
    );
  q_31_FFY_RSTOR : X_BUF
    port map (
      I => q_31_SRMUX_OUTPUTNOT,
      O => q_31_FFY_RST
    );
  q_31_FFY_ASYNC_FF_GSR_OR_70 : X_OR2
    port map (
      I0 => q_31_FFY_RST,
      I1 => GSR,
      O => q_31_FFY_ASYNC_FF_GSR_OR
    );
  q_24_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_24_SRMUX_OUTPUTNOT
    );
  q_23 : X_FF
    port map (
      I => q(24),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_24_FFY_ASYNC_FF_GSR_OR,
      O => q(23)
    );
  q_24_FFY_RSTOR : X_BUF
    port map (
      I => q_24_SRMUX_OUTPUTNOT,
      O => q_24_FFY_RST
    );
  q_24_FFY_ASYNC_FF_GSR_OR_71 : X_OR2
    port map (
      I0 => q_24_FFY_RST,
      I1 => GSR,
      O => q_24_FFY_ASYNC_FF_GSR_OR
    );
  q_24 : X_FF
    port map (
      I => q(25),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_24_FFX_ASYNC_FF_GSR_OR,
      O => q(24)
    );
  q_24_FFX_RSTOR : X_BUF
    port map (
      I => q_24_SRMUX_OUTPUTNOT,
      O => q_24_FFX_RST
    );
  q_24_FFX_ASYNC_FF_GSR_OR_72 : X_OR2
    port map (
      I0 => q_24_FFX_RST,
      I1 => GSR,
      O => q_24_FFX_ASYNC_FF_GSR_OR
    );
  q_16_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_16_SRMUX_OUTPUTNOT
    );
  q_15 : X_FF
    port map (
      I => q(16),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_16_FFY_ASYNC_FF_GSR_OR,
      O => q(15)
    );
  q_16_FFY_RSTOR : X_BUF
    port map (
      I => q_16_SRMUX_OUTPUTNOT,
      O => q_16_FFY_RST
    );
  q_16_FFY_ASYNC_FF_GSR_OR_73 : X_OR2
    port map (
      I0 => q_16_FFY_RST,
      I1 => GSR,
      O => q_16_FFY_ASYNC_FF_GSR_OR
    );
  q_16 : X_FF
    port map (
      I => q(17),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_16_FFX_ASYNC_FF_GSR_OR,
      O => q(16)
    );
  q_16_FFX_RSTOR : X_BUF
    port map (
      I => q_16_SRMUX_OUTPUTNOT,
      O => q_16_FFX_RST
    );
  q_16_FFX_ASYNC_FF_GSR_OR_74 : X_OR2
    port map (
      I0 => q_16_FFX_RST,
      I1 => GSR,
      O => q_16_FFX_ASYNC_FF_GSR_OR
    );
  y_increment_1_OBUF_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => y_increment_1_OBUF_SRMUX_OUTPUTNOT
    );
  y_increment_1 : X_FF
    port map (
      I => q(24),
      CE => m2_state_FFD5,
      CLK => clk_BUFGP,
      SET => GND,
      RST => y_increment_1_OBUF_FFY_ASYNC_FF_GSR_OR,
      O => y_increment_1_OBUF
    );
  y_increment_1_OBUF_FFY_RSTOR : X_BUF
    port map (
      I => y_increment_1_OBUF_SRMUX_OUTPUTNOT,
      O => y_increment_1_OBUF_FFY_RST
    );
  y_increment_1_OBUF_FFY_ASYNC_FF_GSR_OR_75 : X_OR2
    port map (
      I0 => y_increment_1_OBUF_FFY_RST,
      I1 => GSR,
      O => y_increment_1_OBUF_FFY_ASYNC_FF_GSR_OR
    );
  q_32_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_32_SRMUX_OUTPUTNOT
    );
  q_32 : X_FF
    port map (
      I => N272,
      CE => m1_state_FFD2_1,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_32_FFY_ASYNC_FF_GSR_OR,
      O => q(32)
    );
  q_32_FFY_RSTOR : X_BUF
    port map (
      I => q_32_SRMUX_OUTPUTNOT,
      O => q_32_FFY_RST
    );
  q_32_FFY_ASYNC_FF_GSR_OR_76 : X_OR2
    port map (
      I0 => q_32_FFY_RST,
      I1 => GSR,
      O => q_32_FFY_ASYNC_FF_GSR_OR
    );
  y_increment_2_OBUF_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => y_increment_2_OBUF_SRMUX_OUTPUTNOT
    );
  y_increment_2 : X_FF
    port map (
      I => q(25),
      CE => m2_state_FFD5,
      CLK => clk_BUFGP,
      SET => GND,
      RST => y_increment_2_OBUF_FFY_ASYNC_FF_GSR_OR,
      O => y_increment_2_OBUF
    );
  y_increment_2_OBUF_FFY_RSTOR : X_BUF
    port map (
      I => y_increment_2_OBUF_SRMUX_OUTPUTNOT,
      O => y_increment_2_OBUF_FFY_RST
    );
  y_increment_2_OBUF_FFY_ASYNC_FF_GSR_OR_77 : X_OR2
    port map (
      I0 => y_increment_2_OBUF_FFY_RST,
      I1 => GSR,
      O => y_increment_2_OBUF_FFY_ASYNC_FF_GSR_OR
    );
  q_26_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_26_SRMUX_OUTPUTNOT
    );
  q_25 : X_FF
    port map (
      I => q(26),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_26_FFY_ASYNC_FF_GSR_OR,
      O => q(25)
    );
  q_26_FFY_RSTOR : X_BUF
    port map (
      I => q_26_SRMUX_OUTPUTNOT,
      O => q_26_FFY_RST
    );
  q_26_FFY_ASYNC_FF_GSR_OR_78 : X_OR2
    port map (
      I0 => q_26_FFY_RST,
      I1 => GSR,
      O => q_26_FFY_ASYNC_FF_GSR_OR
    );
  q_26 : X_FF
    port map (
      I => q(27),
      CE => m1_state_FFD2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_26_FFX_ASYNC_FF_GSR_OR,
      O => q(26)
    );
  q_26_FFX_RSTOR : X_BUF
    port map (
      I => q_26_SRMUX_OUTPUTNOT,
      O => q_26_FFX_RST
    );
  q_26_FFX_ASYNC_FF_GSR_OR_79 : X_OR2
    port map (
      I0 => q_26_FFX_RST,
      I1 => GSR,
      O => q_26_FFX_ASYNC_FF_GSR_OR
    );
  q_18_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => q_18_SRMUX_OUTPUTNOT
    );
  q_17 : X_FF
    port map (
      I => q(18),
      CE => m1_state_FFD2_2,
      CLK => clk_BUFGP,
      SET => GND,
      RST => q_18_FFY_ASYNC_FF_GSR_OR,
      O => q(17)
    );
  q_18_FFY_RSTOR : X_BUF
    port map (
      I => q_18_SRMUX_OUTPUTNOT,
      O => q_18_FFY_RST
    );
  q_18_FFY_ASYNC_F