mouse_timesim.vhd

用vhdl实现ps2鼠标的源程序

    port map (
      I0 => m2_state_FFD4_FFY_RST,
      I1 => GSR,
      O => m2_state_FFD4_FFY_ASYNC_FF_GSR_OR
    );
  m2_state_FFD4_37 : X_FF
    port map (
      I => N375,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD4_FFX_ASYNC_FF_GSR_OR,
      O => m2_state_FFD4
    );
  m2_state_FFD4_FFX_RSTOR : X_BUF
    port map (
      I => m2_state_FFD4_SRMUX_OUTPUTNOT,
      O => m2_state_FFD4_FFX_RST
    );
  m2_state_FFD4_FFX_ASYNC_FF_GSR_OR_38 : X_OR2
    port map (
      I0 => m2_state_FFD4_FFX_RST,
      I1 => GSR,
      O => m2_state_FFD4_FFX_ASYNC_FF_GSR_OR
    );
  I_m2_state_XX_FFD9 : X_LUT4
    generic map(
      INIT => X"FF30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N329,
      ADR2 => m2_state_FFD9,
      ADR3 => N344,
      O => N348
    );
  I_4_LUT_18 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => m2_state_FFD8,
      ADR1 => N2316,
      ADR2 => bitcount(3),
      ADR3 => N313,
      O => m2_state_FFD9_FROM
    );
  m2_state_FFD9_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m2_state_FFD9_SRMUX_OUTPUTNOT
    );
  m2_state_FFD9_XUSED : X_BUF
    port map (
      I => m2_state_FFD9_FROM,
      O => N344
    );
  m2_state_FFD9_39 : X_FF
    port map (
      I => N348,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD9_FFY_ASYNC_FF_GSR_OR,
      O => m2_state_FFD9
    );
  m2_state_FFD9_FFY_RSTOR : X_BUF
    port map (
      I => m2_state_FFD9_SRMUX_OUTPUTNOT,
      O => m2_state_FFD9_FFY_RST
    );
  m2_state_FFD9_FFY_ASYNC_FF_GSR_OR_40 : X_OR2
    port map (
      I0 => m2_state_FFD9_FFY_RST,
      I1 => GSR,
      O => m2_state_FFD9_FFY_ASYNC_FF_GSR_OR
    );
  I_m1_state_XX_FFD2 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => N271,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => m1_state_FFD1,
      O => m1_state_FFD2_2_GROM
    );
  m1_state_FFD2_2_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m1_state_FFD2_2_SRMUX_OUTPUTNOT
    );
  m1_state_FFD2_2_YUSED : X_BUF
    port map (
      I => m1_state_FFD2_2_GROM,
      O => N282
    );
  m1_state_FFD2_1_41 : X_FF
    port map (
      I => m1_state_FFD2_2_GROM,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m1_state_FFD2_2_FFY_ASYNC_FF_GSR_OR,
      O => m1_state_FFD2_1
    );
  m1_state_FFD2_2_FFY_RSTOR : X_BUF
    port map (
      I => m1_state_FFD2_2_SRMUX_OUTPUTNOT,
      O => m1_state_FFD2_2_FFY_RST
    );
  m1_state_FFD2_2_FFY_ASYNC_FF_GSR_OR_42 : X_OR2
    port map (
      I0 => m1_state_FFD2_2_FFY_RST,
      I1 => GSR,
      O => m1_state_FFD2_2_FFY_ASYNC_FF_GSR_OR
    );
  m1_state_FFD2_2_43 : X_FF
    port map (
      I => N282,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m1_state_FFD2_2_FFX_ASYNC_FF_GSR_OR,
      O => m1_state_FFD2_2
    );
  m1_state_FFD2_2_FFX_RSTOR : X_BUF
    port map (
      I => m1_state_FFD2_2_SRMUX_OUTPUTNOT,
      O => m1_state_FFD2_2_FFX_RST
    );
  m1_state_FFD2_2_FFX_ASYNC_FF_GSR_OR_44 : X_OR2
    port map (
      I0 => m1_state_FFD2_2_FFX_RST,
      I1 => GSR,
      O => m1_state_FFD2_2_FFX_ASYNC_FF_GSR_OR
    );
  I_m2_state_XX_FFD10 : X_LUT4
    generic map(
      INIT => X"88F8"
    )
    port map (
      ADR0 => m2_state_FFD9,
      ADR1 => N329,
      ADR2 => m2_state_FFD10,
      ADR3 => N319,
      O => N334
    );
  I_XXL_187 : X_LUT4
    generic map(
      INIT => X"0008"
    )
    port map (
      ADR0 => N2340,
      ADR1 => m1_state_FFD2,
      ADR2 => bitcount(0),
      ADR3 => bitcount(5),
      O => m2_state_FFD10_FROM
    );
  m2_state_FFD10_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m2_state_FFD10_SRMUX_OUTPUTNOT
    );
  m2_state_FFD10_XUSED : X_BUF
    port map (
      I => m2_state_FFD10_FROM,
      O => N319
    );
  m2_state_FFD10_45 : X_FF
    port map (
      I => N334,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD10_FFY_ASYNC_FF_GSR_OR,
      O => m2_state_FFD10
    );
  m2_state_FFD10_FFY_RSTOR : X_BUF
    port map (
      I => m2_state_FFD10_SRMUX_OUTPUTNOT,
      O => m2_state_FFD10_FFY_RST
    );
  m2_state_FFD10_FFY_ASYNC_FF_GSR_OR_46 : X_OR2
    port map (
      I0 => m2_state_FFD10_FFY_RST,
      I1 => GSR,
      O => m2_state_FFD10_FFY_ASYNC_FF_GSR_OR
    );
  I_m2_state_XX_FFD11 : X_LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      ADR0 => N317,
      ADR1 => N2310,
      ADR2 => bitcount(2),
      ADR3 => N2312,
      O => N325
    );
  I_XXL_187_SW1 : X_LUT4
    generic map(
      INIT => X"B3A0"
    )
    port map (
      ADR0 => m2_state_FFD10,
      ADR1 => m1_state_FFD2_1,
      ADR2 => bitcount(3),
      ADR3 => m2_state_FFD11,
      O => m2_state_FFD11_FROM
    );
  m2_state_FFD11_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m2_state_FFD11_SRMUX_OUTPUTNOT
    );
  m2_state_FFD11_XUSED : X_BUF
    port map (
      I => m2_state_FFD11_FROM,
      O => N2312
    );
  m2_state_FFD11_47 : X_FF
    port map (
      I => N325,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD11_FFY_ASYNC_FF_GSR_OR,
      O => m2_state_FFD11
    );
  m2_state_FFD11_FFY_RSTOR : X_BUF
    port map (
      I => m2_state_FFD11_SRMUX_OUTPUTNOT,
      O => m2_state_FFD11_FFY_RST
    );
  m2_state_FFD11_FFY_ASYNC_FF_GSR_OR_48 : X_OR2
    port map (
      I0 => m2_state_FFD11_FFY_RST,
      I1 => GSR,
      O => m2_state_FFD11_FFY_ASYNC_FF_GSR_OR
    );
  I_m2_state_XX_FFD13 : X_LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      ADR0 => N272,
      ADR1 => m2_state_FFD12,
      ADR2 => m1_state_FFD2_1,
      ADR3 => m2_state_FFD13,
      O => N297
    );
  I_m2_state_XX_FFD14 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => m2_state_FFD12,
      ADR1 => N272,
      ADR2 => m1_state_FFD2_1,
      ADR3 => VCC,
      O => N292
    );
  m2_state_FFD14_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m2_state_FFD14_SRMUX_OUTPUTNOT
    );
  m2_state_FFD13_49 : X_FF
    port map (
      I => N297,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD14_FFY_ASYNC_FF_GSR_OR,
      O => m2_state_FFD13
    );
  m2_state_FFD14_FFY_RSTOR : X_BUF
    port map (
      I => m2_state_FFD14_SRMUX_OUTPUTNOT,
      O => m2_state_FFD14_FFY_RST
    );
  m2_state_FFD14_FFY_ASYNC_FF_GSR_OR_50 : X_OR2
    port map (
      I0 => m2_state_FFD14_FFY_RST,
      I1 => GSR,
      O => m2_state_FFD14_FFY_ASYNC_FF_GSR_OR
    );
  m2_state_FFD14_51 : X_FF
    port map (
      I => N292,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD14_FFX_ASYNC_FF_GSR_OR,
      O => m2_state_FFD14
    );
  m2_state_FFD14_FFX_RSTOR : X_BUF
    port map (
      I => m2_state_FFD14_SRMUX_OUTPUTNOT,
      O => m2_state_FFD14_FFX_RST
    );
  m2_state_FFD14_FFX_ASYNC_FF_GSR_OR_52 : X_OR2
    port map (
      I0 => m2_state_FFD14_FFX_RST,
      I1 => GSR,
      O => m2_state_FFD14_FFX_ASYNC_FF_GSR_OR
    );
  I_m1_state_XX_FFD5 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => N271,
      ADR3 => m1_state_FFD4,
      O => N273
    );
  I_m1_state_XX_FFD6 : X_LUT4
    generic map(
      INIT => X"EEAE"
    )
    port map (
      ADR0 => m1_state_FFD5,
      ADR1 => m1_state_FFD6,
      ADR2 => debounce_timer_count(0),
      ADR3 => debounce_timer_count(1),
      O => N269
    );
  m1_state_FFD6_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m1_state_FFD6_SRMUX_OUTPUTNOT
    );
  m1_state_FFD5_53 : X_FF
    port map (
      I => N273,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m1_state_FFD6_FFY_ASYNC_FF_GSR_OR,
      O => m1_state_FFD5
    );
  m1_state_FFD6_FFY_RSTOR : X_BUF
    port map (
      I => m1_state_FFD6_SRMUX_OUTPUTNOT,
      O => m1_state_FFD6_FFY_RST
    );
  m1_state_FFD6_FFY_ASYNC_FF_GSR_OR_54 : X_OR2
    port map (
      I0 => m1_state_FFD6_FFY_RST,
      I1 => GSR,
      O => m1_state_FFD6_FFY_ASYNC_FF_GSR_OR
    );
  m1_state_FFD6_55 : X_FF
    port map (
      I => N269,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m1_state_FFD6_FFX_ASYNC_FF_GSR_OR,
      O => m1_state_FFD6
    );
  m1_state_FFD6_FFX_RSTOR : X_BUF
    port map (
      I => m1_state_FFD6_SRMUX_OUTPUTNOT,
      O => m1_state_FFD6_FFX_RST
    );
  m1_state_FFD6_FFX_ASYNC_FF_GSR_OR_56 : X_OR2
    port map (
      I0 => m1_state_FFD6_FFX_RST,
      I1 => GSR,
      O => m1_state_FFD6_FFX_ASYNC_FF_GSR_OR
    );
  I_XXL_186 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => bitcount(0),
      ADR1 => m1_state_FFD2,
      ADR2 => bitcount(5),
      ADR3 => N2336,
      O => N2336_GROM
    );
  I_XXL_189_SW0 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => bitcount(1),
      ADR1 => bitcount(3),
      ADR2 => bitcount(4),
      ADR3 => bitcount(2),
      O => N2336_FROM
    );
  N2336_YUSED : X_BUF
    port map (
      I => N2336_GROM,
      O => N329
    );
  N2336_XUSED : X_BUF
    port map (
      I => N2336_FROM,
      O => N2336
    );
  I_debounce_timer_count_ClkEn_INV : X_LUT4
    generic map(
      INIT => X"FF33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => debounce_timer_count(0),
      ADR2 => VCC,
      ADR3 => debounce_timer_count(1),
      O => m1_state_FFD3_GROM
    );
  I_m1_state_XX_FFD3 : X_LUT4
    generic map(
      INIT => X"FABA"
    )
    port map (
      ADR0 => m1_state_FFD2_1,
      ADR1 => debounce_timer_count(0),
      ADR2 => m1_state_FFD3,
      ADR3 => debounce_timer_count(1),
      O => N260
    );
  m1_state_FFD3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m1_state_FFD3_SRMUX_OUTPUTNOT
    );
  m1_state_FFD3_YUSED : X_BUF
    port map (
      I => m1_state_FFD3_GROM,
      O => N258
    );
  m1_state_FFD3_57 : X_FF
    port map (
      I => N260,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m1_state_FFD3_FFX_ASYNC_FF_GSR_OR,
      O => m1_state_FFD3
    );
  m1_state_FFD3_FFX_RSTOR : X_BUF
    port map (
      I => m1_state_FFD3_SRMUX_OUTPUTNOT,
      O => m1_state_FFD3_FFX_RST
    );
  m1_state_FFD3_FFX_ASYNC_FF_GSR_OR_58 : X_OR2
    port map (
      I0 => m1_state_FFD3_FFX_RST,
      I1 => GSR,
      O => m1_state_FFD3_FFX_ASYNC_FF_GSR_OR
    );
  I_m2_state_XX_FFD6 : X_LUT4
    generic map(
      INIT => X"EAEA"
    )
    port map (
      ADR0 => m2_state_FFD1,
      ADR1 => m2_state_FFD6,