mouse_timesim.vhd

用vhdl实现ps2鼠标的源程序

      O => Madd_n0033_inst_lut2_0
    );
  Madd_n0033_inst_cy_0_18 : X_MUX2
    port map (
      IA => GLOBAL_LOGIC1_0,
      IB => N393_CYINIT,
      SEL => Madd_n0033_inst_lut2_0,
      O => Madd_n0033_inst_cy_0
    );
  N393_CYINIT_19 : X_BUF
    port map (
      I => N393_LOGIC_ZERO,
      O => N393_CYINIT
    );
  N393_YUSED : X_BUF
    port map (
      I => N393_XORG,
      O => N393
    );
  N393_COUTUSED : X_BUF
    port map (
      I => N393_CYMUXG,
      O => Madd_n0033_inst_cy_1
    );
  N393_LOGIC_ZERO_20 : X_ZERO
    port map (
      O => N393_LOGIC_ZERO
    );
  Madd_n0033_inst_sum_3 : X_XOR2
    port map (
      I0 => Madd_n0033_inst_cy_2,
      I1 => N385_GROM,
      O => N385_XORG
    );
  Madd_n0033_inst_cy_3_21 : X_MUX2
    port map (
      IA => N385_LOGIC_ZERO,
      IB => Madd_n0033_inst_cy_2,
      SEL => N385_GROM,
      O => N385_CYMUXG
    );
  N385_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => bitcount(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => N385_GROM
    );
  N385_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => bitcount(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N385_FROM
    );
  Madd_n0033_inst_sum_2 : X_XOR2
    port map (
      I0 => N385_CYINIT,
      I1 => N385_FROM,
      O => N385_XORF
    );
  Madd_n0033_inst_cy_2_22 : X_MUX2
    port map (
      IA => N385_LOGIC_ZERO,
      IB => N385_CYINIT,
      SEL => N385_FROM,
      O => Madd_n0033_inst_cy_2
    );
  N385_CYINIT_23 : X_BUF
    port map (
      I => Madd_n0033_inst_cy_1,
      O => N385_CYINIT
    );
  N385_LOGIC_ZERO_24 : X_ZERO
    port map (
      O => N385_LOGIC_ZERO
    );
  N385_YUSED : X_BUF
    port map (
      I => N385_XORG,
      O => N397
    );
  N385_XUSED : X_BUF
    port map (
      I => N385_XORF,
      O => N385
    );
  N385_COUTUSED : X_BUF
    port map (
      I => N385_CYMUXG,
      O => Madd_n0033_inst_cy_3
    );
  Madd_n0033_inst_sum_5 : X_XOR2
    port map (
      I0 => Madd_n0033_inst_cy_4,
      I1 => bitcount_5_rt,
      O => N401_XORG
    );
  bitcount_5_rt_25 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => bitcount(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => bitcount_5_rt
    );
  N401_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => bitcount(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N401_FROM
    );
  Madd_n0033_inst_sum_4 : X_XOR2
    port map (
      I0 => N401_CYINIT,
      I1 => N401_FROM,
      O => N401_XORF
    );
  Madd_n0033_inst_cy_4_26 : X_MUX2
    port map (
      IA => N401_LOGIC_ZERO,
      IB => N401_CYINIT,
      SEL => N401_FROM,
      O => Madd_n0033_inst_cy_4
    );
  N401_CYINIT_27 : X_BUF
    port map (
      I => Madd_n0033_inst_cy_3,
      O => N401_CYINIT
    );
  N401_YUSED : X_BUF
    port map (
      I => N401_XORG,
      O => N249
    );
  N401_XUSED : X_BUF
    port map (
      I => N401_XORF,
      O => N401
    );
  N401_LOGIC_ZERO_28 : X_ZERO
    port map (
      O => N401_LOGIC_ZERO
    );
  I_XXL_190 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => bitcount(2),
      ADR1 => bitcount(3),
      ADR2 => bitcount(1),
      ADR3 => N313,
      O => N313_GROM
    );
  I_XXL_191 : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => m1_state_FFD2_1,
      ADR1 => bitcount(5),
      ADR2 => VCC,
      ADR3 => bitcount(4),
      O => N313_FROM
    );
  N313_YUSED : X_BUF
    port map (
      I => N313_GROM,
      O => N342
    );
  N313_XUSED : X_BUF
    port map (
      I => N313_FROM,
      O => N313
    );
  I_watchdog_timer_count_ClkEn_INV : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => N228,
      ADR1 => N234,
      ADR2 => N222,
      ADR3 => N242,
      O => N242_GROM
    );
  I_3_LUT_9 : X_LUT4
    generic map(
      INIT => X"FFF5"
    )
    port map (
      ADR0 => watchdog_timer_count(7),
      ADR1 => VCC,
      ADR2 => watchdog_timer_count(6),
      ADR3 => watchdog_timer_count(5),
      O => N242_FROM
    );
  N242_YUSED : X_BUF
    port map (
      I => N242_GROM,
      O => N244
    );
  N242_XUSED : X_BUF
    port map (
      I => N242_FROM,
      O => N242
    );
  I_n0027_0 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => m1_state_FFD2_1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => bitcount(0),
      O => N391
    );
  I_n0027_1 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N393,
      ADR2 => VCC,
      ADR3 => m1_state_FFD2_1,
      O => N395
    );
  bitcount_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => bitcount_1_SRMUX_OUTPUTNOT
    );
  bitcount_0 : X_FF
    port map (
      I => N391,
      CE => N247,
      CLK => clk_BUFGP,
      SET => GND,
      RST => bitcount_1_FFY_ASYNC_FF_GSR_OR,
      O => bitcount(0)
    );
  bitcount_1_FFY_RSTOR : X_BUF
    port map (
      I => bitcount_1_SRMUX_OUTPUTNOT,
      O => bitcount_1_FFY_RST
    );
  bitcount_1_FFY_ASYNC_FF_GSR_OR_29 : X_OR2
    port map (
      I0 => bitcount_1_FFY_RST,
      I1 => GSR,
      O => bitcount_1_FFY_ASYNC_FF_GSR_OR
    );
  bitcount_1 : X_FF
    port map (
      I => N395,
      CE => N247,
      CLK => clk_BUFGP,
      SET => GND,
      RST => bitcount_1_FFX_ASYNC_FF_GSR_OR,
      O => bitcount(1)
    );
  bitcount_1_FFX_RSTOR : X_BUF
    port map (
      I => bitcount_1_SRMUX_OUTPUTNOT,
      O => bitcount_1_FFX_RST
    );
  bitcount_1_FFX_ASYNC_FF_GSR_OR_30 : X_OR2
    port map (
      I0 => bitcount_1_FFX_RST,
      I1 => GSR,
      O => bitcount_1_FFX_ASYNC_FF_GSR_OR
    );
  I_n0027_2 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => m1_state_FFD2_1,
      ADR1 => N385,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N387
    );
  I_n0027_3 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => N397,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => m1_state_FFD2_1,
      O => N399
    );
  bitcount_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => bitcount_3_SRMUX_OUTPUTNOT
    );
  bitcount_2 : X_FF
    port map (
      I => N387,
      CE => N247,
      CLK => clk_BUFGP,
      SET => GND,
      RST => bitcount_3_FFY_ASYNC_FF_GSR_OR,
      O => bitcount(2)
    );
  bitcount_3_FFY_RSTOR : X_BUF
    port map (
      I => bitcount_3_SRMUX_OUTPUTNOT,
      O => bitcount_3_FFY_RST
    );
  bitcount_3_FFY_ASYNC_FF_GSR_OR_31 : X_OR2
    port map (
      I0 => bitcount_3_FFY_RST,
      I1 => GSR,
      O => bitcount_3_FFY_ASYNC_FF_GSR_OR
    );
  bitcount_3 : X_FF
    port map (
      I => N399,
      CE => N247,
      CLK => clk_BUFGP,
      SET => GND,
      RST => bitcount_3_FFX_ASYNC_FF_GSR_OR,
      O => bitcount(3)
    );
  bitcount_3_FFX_RSTOR : X_BUF
    port map (
      I => bitcount_3_SRMUX_OUTPUTNOT,
      O => bitcount_3_FFX_RST
    );
  bitcount_3_FFX_ASYNC_FF_GSR_OR_32 : X_OR2
    port map (
      I0 => bitcount_3_FFX_RST,
      I1 => GSR,
      O => bitcount_3_FFX_ASYNC_FF_GSR_OR
    );
  I_n0027_4 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => N401,
      ADR3 => m1_state_FFD2_1,
      O => N403
    );
  I_n0027_5 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => m1_state_FFD2_1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => N249,
      O => N251
    );
  bitcount_5_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => bitcount_5_SRMUX_OUTPUTNOT
    );
  bitcount_4 : X_FF
    port map (
      I => N403,
      CE => N247,
      CLK => clk_BUFGP,
      SET => GND,
      RST => bitcount_5_FFY_ASYNC_FF_GSR_OR,
      O => bitcount(4)
    );
  bitcount_5_FFY_RSTOR : X_BUF
    port map (
      I => bitcount_5_SRMUX_OUTPUTNOT,
      O => bitcount_5_FFY_RST
    );
  bitcount_5_FFY_ASYNC_FF_GSR_OR_33 : X_OR2
    port map (
      I0 => bitcount_5_FFY_RST,
      I1 => GSR,
      O => bitcount_5_FFY_ASYNC_FF_GSR_OR
    );
  bitcount_5 : X_FF
    port map (
      I => N251,
      CE => N247,
      CLK => clk_BUFGP,
      SET => GND,
      RST => bitcount_5_FFX_ASYNC_FF_GSR_OR,
      O => bitcount(5)
    );
  bitcount_5_FFX_RSTOR : X_BUF
    port map (
      I => bitcount_5_SRMUX_OUTPUTNOT,
      O => bitcount_5_FFX_RST
    );
  bitcount_5_FFX_ASYNC_FF_GSR_OR_34 : X_OR2
    port map (
      I0 => bitcount_5_FFX_RST,
      I1 => GSR,
      O => bitcount_5_FFX_ASYNC_FF_GSR_OR
    );
  I_m2_state_XX_FFD3 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => m2_state_FFD2,
      ADR1 => m2_state_FFD3,
      ADR2 => m1_state_FFD2_1,
      ADR3 => N244,
      O => N370
    );
  I_m2_state_XX_FFD4 : X_LUT4
    generic map(
      INIT => X"AFAA"
    )
    port map (
      ADR0 => m2_state_FFD14,
      ADR1 => VCC,
      ADR2 => N244,
      ADR3 => m2_state_FFD3,
      O => N375
    );
  m2_state_FFD4_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => m2_state_FFD4_SRMUX_OUTPUTNOT
    );
  m2_state_FFD3_35 : X_FF
    port map (
      I => N370,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => m2_state_FFD4_FFY_ASYNC_FF_GSR_OR,
      O => m2_state_FFD3
    );
  m2_state_FFD4_FFY_RSTOR : X_BUF
    port map (
      I => m2_state_FFD4_SRMUX_OUTPUTNOT,
      O => m2_state_FFD4_FFY_RST
    );
  m2_state_FFD4_FFY_ASYNC_FF_GSR_OR_36 : X_OR2