test.vhd

用vhdl实现ps2鼠标的源程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
    Port ( reset,clk : in std_logic;
	        ps2_clk : in std_logic;
	        rise,fall : out std_logic);
end test;

architecture Behavioral of test is

type m1statetype is ( m1_clk_h, m1_falling_edge, 
         m1_clk_l, m1_rising_edge);
signal m1_state,m1_next_state : m1statetype;
signal n_rise,n_fall : std_logic;

begin

---------------m1 state State register
m1statechg: process (reset, clk)
begin 
  if (reset='0') then
     rise <= '0';
	  fall <= '0';
     m1_state <= m1_clk_h;
	  --clean_clk <= '0';
  elsif (clk'event and clk='1') then 
     m1_state <= m1_next_state;
	  rise <= n_rise;
	  fall <= n_fall;
  end if;
end process;

-- State transition logic
m1statetr: process (m1_state, ps2_clk)
begin 
  -- Output signals default to this value, unless changed in a state condition.
  n_rise <= '0';
  N_fall <= '0';

  case m1_state is
    when m1_clk_h =>
      if (ps2_clk='0') then
		   m1_next_state <= m1_falling_edge;
      else 
		   m1_next_state <= m1_clk_h;
      end if;
    when m1_falling_edge =>
      n_fall <= '1';
      m1_next_state <= m1_clk_l;--m1_next_state <= m1_falling_wait;
    when m1_clk_l =>
      if (ps2_clk='1') then
		   m1_next_state <= m1_rising_edge;
      else 
		  m1_next_state <= m1_clk_l;
      end if;
    when m1_rising_edge =>
      n_rise <= '1';
      m1_next_state <= m1_clk_h;--m1_next_state <= m1_rising_wait;
    when others => m1_next_state <= m1_clk_h;
  end case;
end process;----------------------------end m1 atate

end Behavioral;