📄 segdecode.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segdecode is
Port ( datain : in std_logic_vector(3 downto 0);
dataout : out std_logic_vector(6 downto 0));
end segdecode;
architecture Behavioral of segdecode is
signal hex : std_logic_vector(6 downto 0);
begin
process (datain)
begin
case datain is -- 0123456
when "0000" => hex <= "0000001";
when "0001" => hex <= "1001111";
when "0010" => hex <= "0010010";
when "0011" => hex <= "0000110";
when "0100" => hex <= "1001100";
when "0101" => hex <= "0100100";
when "0110" => hex <= "0100000";
when "0111" => hex <= "0001111";
when "1000" => hex <= "0000000";
when "1001" => hex <= "0000100";
when "1010" => hex <= "0001000";
when "1011" => hex <= "1100000";
when "1100" => hex <= "0110001";
when "1101" => hex <= "1000010";
when "1110" => hex <= "0110000";
when "1111" => hex <= "0111000";
when others => hex <= "1111111";
end case;
end process;
dataout <= hex;
end Behavioral;
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