📄 ila_dd256_dw16_tw8_e2.edn
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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2002 9 23 11 39 9)
(author "Xilinx, Inc.")
(program "ChipScope Core Generator" (version "v4.1i"))))
(comment "**********************************
Component Name: ila_dd256_dw16_tw8_e2
Device Family: Virtex/VirtexE/Spartan2
Trigger Width: 8
Data Width: 16
Trigger Equals Data: false
Data Depth: 256
Match Units: 2
Extended Matching: true
Use SRL16's: true
Sample on RISING edge of clock
**********************************")
(comment "This file is owned and controlled by Xilinx and must be used
solely for design, simulation, implementation and creation of design files
limited to Xilinx devices or technologies. Use with non-Xilinx devices or
technologies is expressly prohibited and immediately terminates your license.
Xilinx products are not intended for use in life support appliances, devices,
or systems. Use in such applications are expressly prohibited.
Copyright (C) 2001, Xilinx, Inc. All Rights Reserved.")
(comment "Core parameters: ")
(comment "data_width = 16 ")
(comment "ram_type = 0 ")
(comment "use_srl16 = 1 ")
(comment "use_inv_clk = 0 ")
(comment "trig_width = 8 ")
(comment "data_depth = 256 ")
(comment "match_unit_type = 1 ")
(comment "InstanceName = ila ")
(comment "device_family = 0 ")
(comment "trig_same_as_data = 0 ")
(comment "num_match_units = 2 ")
(external xilinxun (edifLevel 0)
(technology (numberDefinition))
(cell VCC (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
(cell GND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell BUF (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell FDE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDPE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port PRE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDR (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDRE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDRS (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port R (direction INPUT))
(port S (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell INV (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT1 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT2 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port O (direction OUTPUT))
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)
)
(cell LUT3 (cellType GENERIC)
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(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port O (direction OUTPUT))
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)
)
(cell LUT4 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MULT_AND (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I1 (direction INPUT))
(port I0 (direction INPUT))
(port LO (direction OUTPUT))
)
)
)
(cell MUXCY_L (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port DI (direction INPUT))
(port CI (direction INPUT))
(port S (direction INPUT))
(port LO (direction OUTPUT))
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)
(cell MUXF5 (cellType GENERIC)
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(port I0 (direction INPUT))
(port I1 (direction INPUT))
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)
)
(cell MUXF6 (cellType GENERIC)
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(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
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)
)
(cell RAMB4_S1_S16 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port WEA (direction INPUT))
(port ENA (direction INPUT))
(port RSTA (direction INPUT))
(port CLKA (direction INPUT))
(port (rename DIA_0_ "DIA<0>") (direction INPUT))
(port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
(port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
(port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
(port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
(port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
(port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
(port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
(port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
(port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
(port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
(port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
(port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
(port (rename ADDRA_11_ "ADDRA<11>") (direction INPUT))
(port WEB (direction INPUT))
(port ENB (direction INPUT))
(port RSTB (direction INPUT))
(port CLKB (direction INPUT))
(port (rename DIB_0_ "DIB<0>") (direction INPUT))
(port (rename DIB_1_ "DIB<1>") (direction INPUT))
(port (rename DIB_2_ "DIB<2>") (direction INPUT))
(port (rename DIB_3_ "DIB<3>") (direction INPUT))
(port (rename DIB_4_ "DIB<4>") (direction INPUT))
(port (rename DIB_5_ "DIB<5>") (direction INPUT))
(port (rename DIB_6_ "DIB<6>") (direction INPUT))
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