mode_control.vhd

用vhdl写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MODE_CONTROL IS
PORT(
     FZ,FC: IN STD_LOGIC;
       DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- IR
Q,CLR,T1,T2,T3,T4: IN STD_LOGIC;
       load,LDPC: OUT STD_LOGIC; --PC
      LDAR: OUT STD_LOGIC; --AR
      LDIR: OUT STD_LOGIC; --IR
LDR0,LDR1,LDR2,R0_B,R1_B,R2_B: OUT STD_LOGIC; --R0,R1,R2
S1,S0,ALU_B,LDAC,LDDR: OUT STD_LOGIC;  --ALU
     WR,CS: OUT STD_LOGIC; --RAM
SW_B,LED_B: OUT STD_LOGIC;
      LDFR: OUT STD_LOGIC --LS74
);
END MODE_CONTROL;

ARCHITECTURE A OF MODE_CONTROL IS
SIGNAL YIMA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL IN1,MOV,CMP,JB,ADD,INC,JMP,OUT1: STD_LOGIC;
SIGNAL RD0,RD1,RD2,RS0,RS1,RS2: STD_LOGIC;
SIGNAL LDRi,RS_B,RD_B: STD_LOGIC;
SIGNAL  M: STD_LOGIC:='0';

BEGIN 
     P1: PROCESS(CLR,T4)
     BEGIN 
         IF(CLR='0') THEN 
             M<='0';
         ELSIF( T4'EVENT AND T4='0') THEN
             IF((IN1 or MOV or JB or INC or JMP or OUT1)='1') THEN
                 M<='0';
             ELSIF((CMP or ADD)='1') THEN
                 M<=NOT M;
             END IF;
         END IF;
     END PROCESS P1;

     P2: PROCESS(Q,CLR)
     BEGIN
         CASE DIN(7 DOWNTO 4) IS
              WHEN "1000"=> YIMA<="00000001";
              WHEN "1001"=> YIMA<="00000010";
              WHEN "1010"=> YIMA<="00000100";
              WHEN "1011"=> YIMA<="00001000";
              WHEN "1100"=> YIMA<="00010000";
              WHEN "1101"=> YIMA<="00100000";
              WHEN "1110"=> YIMA<="01000000";
              WHEN "1111"=> YIMA<="10000000";
            WHEN OTHERS=> YIMA<="00000000";
         END CASE;

         LDAC<=(CMP OR ADD OR INC) AND T3 AND(NOT Q) AND (NOT M);
         LDDR<=(CMP OR ADD)AND T4 AND(NOT Q)AND (NOT M);
         ALU_B<=NOT((ADD AND T1 AND M)OR (INC AND T4 AND (NOT M)));
         load<=NOT((JMP AND T4 AND (NOT M))OR (JB AND T4 AND (NOT M)AND(FC AND (NOT FZ))));
         LDPC<=(T1 AND (NOT Q)AND (NOT M))  OR ((MOV OR JB OR JMP) AND T3 AND (NOT Q) AND (NOT M)) OR (JB AND T4 AND (NOT Q)AND (NOT M)AND (FC AND (NOT FZ)))OR(JMP AND T4 AND(NOT Q)AND (NOT Q)AND (NOT M));
         LDIR<=T2 AND (NOT Q)AND (NOT M);
         LDFR<=CMP AND T1 AND (NOT Q)AND M;
         RS_B<=NOT ((CMP OR ADD OR OUT1)AND T3 AND (NOT M));
         RD_B<=NOT((CMP AND T4 AND (NOT M))OR (ADD AND T4 AND (NOT M))OR (INC AND T3 AND (NOT M)));
         R0_B<=(RS_B OR DIN(3) OR DIN(2)) AND (RD_B OR DIN(1) OR DIN(0));
         R1_B<=(RS_B OR DIN(3) OR (NOT DIN(2))) AND (RD_B OR DIN(1) OR (NOT DIN(0)));
         R2_B<=(RS_B OR (NOT DIN(3))OR DIN(2))  AND  (RD_B OR (NOT DIN(1))OR DIN(0));
         LDRi<=(IN1 AND T3 AND (NOT Q)AND (NOT M))  OR  (MOV AND T4 AND (NOT Q) AND (NOT M))OR (ADD AND T1 AND (NOT Q)AND M) OR (INC AND T4 AND (NOT Q)AND (NOT M));
         LDR0<=LDRi AND (NOT DIN(1)) AND (NOT DIN(0));
         LDR1<=LDRi AND (NOT DIN(1)) AND DIN(0);
         LDR2<=LDRi AND DIN(1) AND (NOT DIN(0)) ;
         S1<=INC AND T4 AND (NOT M);
         S0<=CMP AND T1 AND M;
         CS<=NOT((T2 AND (NOT M)) OR (MOV AND T4 AND (NOT M)) OR (JB AND T4 AND (NOT M) AND (FC AND (NOT FZ))) OR (JMP AND T4 AND (NOT M)));
         WR<=NOT(OUT1 AND T3 AND (NOT Q) AND (NOT M));
       LDAR<=(T1 OR ((MOV OR JB OR JMP)AND T3)) AND (NOT Q) AND (NOT M);
       SW_B<=NOT(IN1 AND T3 AND (NOT M));
      LED_B<=NOT(OUT1 AND T3 AND (NOT M));
   END PROCESS P2;

   OUT1<=YIMA(7);
   JMP<=YIMA(6);
   INC<=YIMA(5);
   ADD<=YIMA(4);
   JB <=YIMA(3);
   CMP<=YIMA(2);
   MOV<=YIMA(1);
   IN1<=YIMA(0);

END A;