📄 rom.rpt
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Project Information d:\xiaoning\rom.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/03/2004 22:23:51
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
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their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
ROM
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
rom EPM7032LC44-6 9 8 0 23 1 71 %
User Pins: 9 8 0
Device-Specific Information: d:\xiaoning\rom.rpt
rom
***** Logic for device 'rom' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
a a R R
d d E E
d d S S
r r E E
e e R R
s s V G G G G G V V
s c s C N N N N N E E
7 s 0 C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
address6 | 7 39 | RESERVED
address5 | 8 38 | RESERVED
address4 | 9 37 | RESERVED
GND | 10 36 | RESERVED
address3 | 11 35 | VCC
address2 | 12 EPM7032LC44-6 34 | RESERVED
address1 | 13 33 | RESERVED
data0 | 14 32 | RESERVED
VCC | 15 31 | RESERVED
data3 | 16 30 | GND
RESERVED | 17 29 | data7
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
d R R R G V d d d R d
a E E E N C a a a E a
t S S S D C t t t S t
a E E E a a a E a
2 R R R 4 1 5 R 6
V V V V
E E E E
D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 12/16( 75%) 3/16( 18%) 14/36( 38%)
B: LC17 - LC32 16/16(100%) 5/16( 31%) 9/16( 56%) 19/36( 52%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 17/32 ( 53%)
Total logic cells used: 23/32 ( 71%)
Total shareable expanders used: 1/32 ( 3%)
Total Turbo logic cells used: 23/32 ( 71%)
Total shareable expanders not available (n/a): 11/32 ( 34%)
Average fan-in: 8.65
Total fan-in: 199
Total input pins required: 9
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 23
Total flipflops required: 0
Total product terms required: 92
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 1
Synthesized logic cells: 15/ 32 ( 46%)
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 6 13 address0
13 (9) (A) INPUT 0 0 0 0 0 6 13 address1
12 (8) (A) INPUT 0 0 0 0 0 6 13 address2
11 (7) (A) INPUT 0 0 0 0 0 6 13 address3
9 (6) (A) INPUT 0 0 0 0 0 6 13 address4
8 (5) (A) INPUT 0 0 0 0 0 6 13 address5
7 (4) (A) INPUT 0 0 0 0 0 6 13 address6
6 (3) (A) INPUT 0 0 0 0 0 6 13 address7
5 (2) (A) INPUT 0 0 0 0 0 8 11 cs
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 10 A OUTPUT t 0 0 0 1 2 0 0 data0
25 31 B OUTPUT t 0 0 0 9 1 0 0 data1
18 13 A OUTPUT t 0 0 0 9 1 0 0 data2
16 11 A OUTPUT t 0 0 0 9 1 0 0 data3
24 32 B OUTPUT t 1 0 1 9 1 0 0 data4
26 30 B OUTPUT t 0 0 0 9 1 0 0 data5
28 28 B OUTPUT t 0 0 0 9 1 0 0 data6
29 27 B OUTPUT t 0 0 0 1 2 0 0 data7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(31) 26 B SOFT s t 1 0 1 8 0 1 0 ~5902~1
(41) 17 B SOFT s t 1 0 1 8 0 1 1 ~6259~1
(40) 18 B LCELL s t 1 1 0 9 1 0 1 ~6279~1~2
(39) 19 B LCELL s t 2 1 1 9 2 1 2 ~6279~1
(38) 20 B LCELL s t 0 0 0 8 1 0 1 ~6285~1~2
(37) 21 B LCELL s t 1 0 1 9 2 1 2 ~6285~1
(36) 22 B LCELL s t 0 0 0 8 1 0 1 ~6291~1~2
(34) 23 B LCELL s t 1 0 1 9 2 1 2 ~6291~1
(33) 24 B LCELL s t 1 0 1 9 1 0 1 ~6297~1~2
(32) 25 B LCELL s t 0 0 0 1 2 0 1 ~6297~1~3
(7) 4 A LCELL s t 1 0 1 9 1 1 2 ~6297~1
(12) 8 A LCELL s t 1 0 1 9 1 1 1 ~6303~1
(17) 12 A LCELL s t 1 0 1 9 1 1 1 ~6309~1
(27) 29 B LCELL s t 1 0 1 9 1 1 1 ~6315~1
(21) 16 A LCELL s t 0 0 0 1 2 1 1 ~6321~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC10 data0
| +----------- LC13 data2
| | +--------- LC11 data3
| | | +------- LC4 ~6297~1
| | | | +----- LC8 ~6303~1
| | | | | +--- LC12 ~6309~1
| | | | | | +- LC16 ~6321~1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B | Logic cells that feed LAB 'A':
LC8 -> - - * - * - - | * - | <-- ~6303~1
LC12 -> - * - - - * - | * - | <-- ~6309~1
LC16 -> * - - - - - * | * - | <-- ~6321~1
Pin
4 -> - * * * * * - | * * | <-- address0
13 -> - * * * * * - | * * | <-- address1
12 -> - * * * * * - | * * | <-- address2
11 -> - * * * * * - | * * | <-- address3
9 -> - * * * * * - | * * | <-- address4
8 -> - * * * * * - | * * | <-- address5
7 -> - * * * * * - | * * | <-- address6
6 -> - * * * * * - | * * | <-- address7
5 -> * * * * * * * | * * | <-- cs
LC17 -> * - - - - - * | * - | <-- ~6259~1
LC25 -> - - - * - - - | * - | <-- ~6297~1~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC31 data1
| +----------------------------- LC32 data4
| | +--------------------------- LC30 data5
| | | +------------------------- LC28 data6
| | | | +----------------------- LC27 data7
| | | | | +--------------------- LC26 ~5902~1
| | | | | | +------------------- LC17 ~6259~1
| | | | | | | +----------------- LC18 ~6279~1~2
| | | | | | | | +--------------- LC19 ~6279~1
| | | | | | | | | +------------- LC20 ~6285~1~2
| | | | | | | | | | +----------- LC21 ~6285~1
| | | | | | | | | | | +--------- LC22 ~6291~1~2
| | | | | | | | | | | | +------- LC23 ~6291~1
| | | | | | | | | | | | | +----- LC24 ~6297~1~2
| | | | | | | | | | | | | | +--- LC25 ~6297~1~3
| | | | | | | | | | | | | | | +- LC29 ~6315~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC26 -> - - - - * - - - - - - - - - - - | - * | <-- ~5902~1
LC18 -> - - - - - - - - * - - - - - - - | - * | <-- ~6279~1~2
LC19 -> - - - - * - - * * - - - - - - - | - * | <-- ~6279~1
LC20 -> - - - - - - - - - - * - - - - - | - * | <-- ~6285~1~2
LC21 -> - - - * - - - - - * * - - - - - | - * | <-- ~6285~1
LC22 -> - - - - - - - - - - - - * - - - | - * | <-- ~6291~1~2
LC23 -> - - * - - - - - - - - * * - - - | - * | <-- ~6291~1
LC24 -> - - - - - - - - - - - - - - * - | - * | <-- ~6297~1~2
LC29 -> * - - - - - - - - - - - - - - * | - * | <-- ~6315~1
Pin
4 -> * * * * - * * * * * * * * * - * | * * | <-- address0
13 -> * * * * - * * * * * * * * * - * | * * | <-- address1
12 -> * * * * - * * * * * * * * * - * | * * | <-- address2
11 -> * * * * - * * * * * * * * * - * | * * | <-- address3
9 -> * * * * - * * * * * * * * * - * | * * | <-- address4
8 -> * * * * - * * * * * * * * * - * | * * | <-- address5
7 -> * * * * - * * * * * * * * * - * | * * | <-- address6
6 -> * * * * - * * * * * * * * * - * | * * | <-- address7
5 -> * * * * * - - * * - * - * * * * | * * | <-- cs
LC4 -> - * - - - - - - - - - - - * * - | - * | <-- ~6297~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\xiaoning\rom.rpt
rom
** EQUATIONS **
address0 : INPUT;
address1 : INPUT;
address2 : INPUT;
address3 : INPUT;
address4 : INPUT;
address5 : INPUT;
address6 : INPUT;
address7 : INPUT;
cs : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', location is LC010, type is output.
data0 = LCELL( _EQ001 $ GND);
_EQ001 = cs & _LC016
# !cs & _LC017;
-- Node name is 'data1'
-- Equation name is 'data1', location is LC031, type is output.
data1 = LCELL( _EQ002 $ GND);
_EQ002 = address0 & address1 & !address2 & !address3 & !address4 &
!address5 & !address6 & !address7 & !cs
# !address0 & !address1 & !address2 & address3 & !address4 &
!address5 & !address6 & !address7 & !cs
# cs & _LC029;
-- Node name is 'data2'
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