📄 pc.rpt
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+----------------------------- LC26 |LPM_ADD_SUB:132|addcore:adder|result_node1
| +--------------------------- LC30 |LPM_ADD_SUB:132|addcore:adder|result_node2
| | +------------------------- LC31 |LPM_ADD_SUB:132|addcore:adder|result_node3
| | | +----------------------- LC25 |LPM_ADD_SUB:132|addcore:adder|result_node4
| | | | +--------------------- LC28 |LPM_ADD_SUB:132|addcore:adder|result_node5
| | | | | +------------------- LC27 |LPM_ADD_SUB:132|addcore:adder|result_node6
| | | | | | +----------------- LC29 |LPM_ADD_SUB:132|addcore:adder|result_node7
| | | | | | | +--------------- LC24 O0
| | | | | | | | +------------- LC23 O1
| | | | | | | | | +----------- LC17 O2
| | | | | | | | | | +--------- LC18 O3
| | | | | | | | | | | +------- LC19 O4
| | | | | | | | | | | | +----- LC20 O5
| | | | | | | | | | | | | +--- LC21 O6
| | | | | | | | | | | | | | +- LC22 O7
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC26 -> - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node1
LC30 -> - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node2
LC31 -> - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node3
LC25 -> - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node4
LC28 -> - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node5
LC27 -> - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node6
LC29 -> - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:132|addcore:adder|result_node7
LC24 -> * * * * * * * * - - - - - - - | - * | <-- O0
LC23 -> * * * * * * * - - - - - - - - | - * | <-- O1
LC17 -> - * * * * * * - - - - - - - - | - * | <-- O2
LC18 -> - - * * * * * - - - - - - - - | - * | <-- O3
LC19 -> - - - * * * * - - - - - - - - | - * | <-- O4
LC20 -> - - - - * * * - - - - - - - - | - * | <-- O5
LC21 -> - - - - - * * - - - - - - - - | - * | <-- O6
LC22 -> - - - - - - * - - - - - - - - | - * | <-- O7
Pin
1 -> - - - - - - - - - - - - - - - | - - | <-- CLR
13 -> - - - - - - - * - - - - - - - | - * | <-- D0
12 -> - - - - - - - - * - - - - - - | - * | <-- D1
11 -> - - - - - - - - - * - - - - - | - * | <-- D2
9 -> - - - - - - - - - - * - - - - | - * | <-- D3
8 -> - - - - - - - - - - - * - - - | - * | <-- D4
7 -> - - - - - - - - - - - - * - - | - * | <-- D5
6 -> - - - - - - - - - - - - - * - | - * | <-- D6
5 -> - - - - - - - - - - - - - - * | - * | <-- D7
43 -> - - - - - - - - - - - - - - - | - - | <-- LDPC
4 -> - - - - - - - * * * * * * * * | - * | <-- LOAD
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\xiaoning\pc.rpt
pc
** EQUATIONS **
CLR : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
LDPC : INPUT;
LOAD : INPUT;
-- Node name is 'O0' = 'qout0'
-- Equation name is 'O0', location is LC024, type is output.
O0 = DFFE( _EQ001 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ001 = LOAD & !O0
# D0 & !LOAD;
-- Node name is 'O1' = 'qout1'
-- Equation name is 'O1', location is LC023, type is output.
O1 = DFFE( _EQ002 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ002 = _LC026 & LOAD
# D1 & !LOAD;
-- Node name is 'O2' = 'qout2'
-- Equation name is 'O2', location is LC017, type is output.
O2 = DFFE( _EQ003 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ003 = _LC030 & LOAD
# D2 & !LOAD;
-- Node name is 'O3' = 'qout3'
-- Equation name is 'O3', location is LC018, type is output.
O3 = DFFE( _EQ004 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ004 = _LC031 & LOAD
# D3 & !LOAD;
-- Node name is 'O4' = 'qout4'
-- Equation name is 'O4', location is LC019, type is output.
O4 = DFFE( _EQ005 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ005 = _LC025 & LOAD
# D4 & !LOAD;
-- Node name is 'O5' = 'qout5'
-- Equation name is 'O5', location is LC020, type is output.
O5 = DFFE( _EQ006 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ006 = _LC028 & LOAD
# D5 & !LOAD;
-- Node name is 'O6' = 'qout6'
-- Equation name is 'O6', location is LC021, type is output.
O6 = DFFE( _EQ007 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ007 = _LC027 & LOAD
# D6 & !LOAD;
-- Node name is 'O7' = 'qout7'
-- Equation name is 'O7', location is LC022, type is output.
O7 = DFFE( _EQ008 $ GND, GLOBAL( LDPC), GLOBAL( CLR), VCC, VCC);
_EQ008 = _LC029 & LOAD
# D7 & !LOAD;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( O1 $ O0);
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( O2 $ _EQ009);
_EQ009 = O0 & O1;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( O3 $ _EQ010);
_EQ010 = O0 & O1 & O2;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( O4 $ _EQ011);
_EQ011 = O0 & O1 & O2 & O3;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( O5 $ _EQ012);
_EQ012 = O0 & O1 & O2 & O3 & O4;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( O6 $ _EQ013);
_EQ013 = O0 & O1 & O2 & O3 & O4 & O5;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( O7 $ _EQ014);
_EQ014 = O0 & O1 & O2 & O3 & O4 & O5 & O6;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\xiaoning\pc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,401K
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