mux4.vhd

来自「用vhdl写的」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX4 IS
PORT(
  A,B,C,D: in std_logic;
  X1,X2,X3,X4: in std_logic_vector(7 downto 0);
  W: OUT std_logic_vector(7 downto 0)
 );
END mux4;

ARCHITECTURE ONE OF MUX4 IS
signal sel: std_logic_vector(3 downto 0);
 BEGIN
    sel<=D&C&B&A;
    process(sel)
    BEGIN
     if (sel="1110") then   --RO_B
       w<=X1;
     elsif (sel="1101") then --R1_B
       w<=x2;
	 elsif (sel="1011") then --R2_B
       w<=x3;
	 elsif (sel="0111") then --ALU_B
       w<=x4;
     else
       w<="00000000";
    end if;
    END process;
 END one;