pc.vhd

来自「用vhdl写的」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--
ENTITY PC IS
PORT(
  LOAD,LDPC,CLR: in std_logic;
  D: in std_logic_vector(7 downto 0);
  O: OUT std_logic_vector(7 downto 0)
 );
END PC;

ARCHITECTURE A OF PC IS
signal qout: std_logic_vector(7 downto 0);
 BEGIN
   process(ldpc,clr,load)
    BEGIN
     if (clr='0') then 
       qout<="00000000";
     elsif (ldpc'event and ldpc='1') then
       if (load='0') then
         qout<=D;             --BUS->PC
       else
         qout<=qout+1;        --PC+1
       end if;
    end if;
   END process;
   o<=qout;
 END A;