mux4vhd.vhd

来自「用vhdl写的」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX4 IS
PORT(
  S1,S2:IN STD_LOGIC;
  X1,X2,X3,X4:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  W:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MUX4;
ARCHITECTURE A OF MUX4 IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
   SEL<=S1&S2;
PROCESS(S1,S2,X1,X2,X3,X4)
BEGIN
CASE SEL IS
  WHEN "00"=>W<=X1;
  WHEN "01"=>W<=X2;
  WHEN "10"=>W<=X3;
  WHEN "11"=>W<=X4;
  WHEN OTHERS=>W<="ZZZZZZZZ";
END CASE;
END PROCESS;
END A;