rom1.tdf

用vhdl写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_unsigned.all;

ENTITY rom IS
PORT(
  cs : in std_logic;
  address: in std_logic_vector(7 downto 0);
  data: out std_logic_vector(7 downto 0)
  );
END rom;

ARCHITECTURE ONE OF rom1 IS
--subtype vector is bit_vector(7 downto 0);
--type rom_array is array(0 to 1) of bit_vector(7 downto 0);
--constant rom_memory : rom_array :=();
								--1 => "00000000", 
								--2 => "00000000",
								--3 => "00000000", 
								-- => "00000000",
								--5 => "00000000", 
								--6 => "00000000", 
								--7 => "00000000",
								--254 => "00000000",
								--255 => "00000000",
								--OTHERS bit_vector' ("00000001"));
BEGIN
  process(cs,address)
type rom_array is array(0 to 17) of bit_vector(7 downto 0);
   variable rom_memory : rom_array;   
  begin
   rom_memory(0):="10000000";
   rom_memory(1):="10010001";
   rom_memory(2):="00000001";
   rom_memory(3):="10010010";
   rom_memory(4):="00000000";
   rom_memory(5):="10100001";
   rom_memory(6):="10110000";
   rom_memory(7):="00001101";
   rom_memory(8):="11000110";
   rom_memory(9):="11010001";
   rom_memory(10):="11010001";
   rom_memory(11):="11010001";
   rom_memory(12):="11100000";
   rom_memory(13):="00000101";
   rom_memory(14):="11111000";
   rom_memory(15):="11100000";
   rom_memory(16):="00001101";

   if (cs='0') then
       case address(7 downto 0) is 
       when "00000000"  =>data<=to_stdlogicvector(rom_memory(0));
       when "00000001"  =>data<=to_stdlogicvector(rom_memory(1));
	   when "00000010"  =>data<=to_stdlogicvector(rom_memory(2));
	   when "00000011"  =>data<=to_stdlogicvector(rom_memory(3));
	   when "00000100"  =>data<=to_stdlogicvector(rom_memory(4));
	   when "00000101"  =>data<=to_stdlogicvector(rom_memory(5));
       when "00000110"  =>data<=to_stdlogicvector(rom_memory(6));
       when "00000111"  =>data<=to_stdlogicvector(rom_memory(7));
	   when "00001000"  =>data<=to_stdlogicvector(rom_memory(8));
	   when "00001001"  =>data<=to_stdlogicvector(rom_memory(9));
	   when "00001010"  =>data<=to_stdlogicvector(rom_memory(10));
	   when "00001011"  =>data<=to_stdlogicvector(rom_memory(11));
       when "00001100"  =>data<=to_stdlogicvector(rom_memory(12));
       when "00001101"  =>data<=to_stdlogicvector(rom_memory(13));
	   when "00001110"  =>data<=to_stdlogicvector(rom_memory(14));
	   when "00001111"  =>data<=to_stdlogicvector(rom_memory(15));
	   when "00010000"  =>data<=to_stdlogicvector(rom_memory(16));
	   when others =>data<="00000000";
     end case;
   end if;
    --data<=to_stdlogicvector(rom_memory(0));--to_stdlogicvector(rom_memory(conv_integer(address)));
    end process;
end one;
 

--no input data in extern
--  rom_memory(0):="10010000";
--   rom_memory(1):="00001010";
--   rom_memory(2):="10010001";
--   rom_memory(3):="00000001";
--   rom_memory(4):="10010010";
--   rom_memory(5):="00000000";
--  rom_memory(6):="10100001";
--   rom_memory(7):="10110000";
--   rom_memory(8):="00001110";
--   rom_memory(9):="11000110";
--   rom_memory(10):="11010001";
--   rom_memory(11):="11010001";
--   rom_memory(12):="11100000";
--   rom_memory(13):="00000110";
--   rom_memory(14):="11111000";
--  rom_memory(15):="11100000";
--   rom_memory(16):="00001110";