alu.vhd

来自「用vhdl写的」· VHDL 代码 · 共 47 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY ALU IS
PORT(
  s1,s0: in std_logic;
  a: in std_logic_vector(7 downto 0);
  b: in std_logic_vector(7 downto 0);
  bcdout: out std_logic_vector(7 downto 0);
  cy,zi:out std_logic
 );
END ALU;

ARCHITECTURE ONE OF ALU IS
 BEGIN
    process(s1,s0)
    BEGIN
    if (s1='0' and s0='0') then  --add
       bcdout<=A+B;
       cy<='0';
       zi<='0';
    elsif (s1='0' and s0='1') then --cmp(sub)
     bcdout<=a-b;
     if(a<b) then
      cy<='1';
      zi<='0';
     elsif (a=b) then 
       cy<='0';
       zi<='1';
     else
      cy<='0';
      zi<='0';
     end if;
    elsif (s1='1' and s0='0') then --inc
     bcdout<=a+1;
     cy<='0';
     zi<='0';     
    else
       bcdout<="00000000";
       cy<='0';
       zi<='0';
    end if ;
    END process;
 END one;