ls273.vhd

来自「用vhdl写的」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--
ENTITY LS273 IS
PORT(
  D: in std_logic_vector(7 downto 0);
  CLK: in std_logic;
  O: OUT std_logic_vector(7 downto 0)
 );
END LS273;

ARCHITECTURE ONE OF LS273 IS
 BEGIN
    process(clk)
    BEGIN
    if (clk'event and clk='1') then
      o<=D;
   end if;
    END process;
 END one;