📄 rom1.rpt
字号:
- 7 - B 23 OR2 s 2 2 0 1 ~6338~1
- 4 - B 23 OR2 1 3 0 2 :6338
- 8 - B 23 OR2 0 4 0 1 :6359
- 4 - B 24 OR2 0 4 0 1 :6410
- 3 - B 24 AND2 s 0 2 0 1 ~6412~1
- 5 - B 24 OR2 1 3 0 1 :6421
- 8 - B 24 OR2 0 4 0 1 :6425
- 8 - B 20 OR2 0 4 0 1 :6461
- 6 - B 20 OR2 s 1 2 0 1 ~6463~1
- 7 - B 20 OR2 s 0 3 0 1 ~6463~2
- 2 - B 21 OR2 0 4 0 1 :6515
- 1 - B 24 OR2 0 3 0 1 :6584
- 4 - B 21 OR2 1 3 0 2 :6613
- 2 - B 15 OR2 s 1 3 0 6 ~6617~1
- 5 - B 21 OR2 0 4 0 1 :6623
- 6 - B 21 OR2 1 3 0 1 :6629
- 8 - B 21 OR2 0 4 0 1 :6641
- 8 - B 16 OR2 1 2 1 0 :6664
- 4 - B 20 OR2 1 2 1 0 :6670
- 1 - B 21 AND2 s 0 4 0 2 ~6671~1
- 5 - B 20 AND2 s 0 2 0 3 ~6671~2
- 1 - B 23 OR2 1 2 1 0 :6676
- 7 - B 21 OR2 s 1 2 0 2 ~6677~1
- 7 - B 24 OR2 1 2 1 0 :6682
- 1 - B 18 OR2 s 1 2 0 4 ~6683~1
- 1 - B 20 OR2 1 2 1 0 :6688
- 2 - B 20 OR2 1 2 1 0 :6694
- 2 - B 24 AND2 s 0 2 0 1 ~6695~1
- 5 - B 23 OR2 s 1 2 0 3 ~6695~2
- 6 - B 24 OR2 1 2 1 0 :6700
- 3 - B 21 OR2 1 2 1 0 :6706
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\xiaoning\rom1.rpt
rom1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 14/ 96( 14%) 0/ 48( 0%) 18/ 48( 37%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\xiaoning\rom1.rpt
rom1
** EQUATIONS **
address0 : INPUT;
address1 : INPUT;
address2 : INPUT;
address3 : INPUT;
address4 : INPUT;
address5 : INPUT;
address6 : INPUT;
address7 : INPUT;
cs : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC3_B21;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC6_B24;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC2_B20;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC1_B20;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC7_B24;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC1_B23;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC4_B20;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC8_B16;
-- Node name is ':5943'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = LCELL( _EQ001);
_EQ001 = !address0 & address4 & _LC1_B13 & _LC4_B18;
-- Node name is '~5963~1'
-- Equation name is '~5963~1', location is LC4_B16, type is buried.
-- synthesized logic cell
_LC4_B16 = LCELL( _EQ002);
_EQ002 = !address4 & _LC1_B13;
-- Node name is '~5963~2'
-- Equation name is '~5963~2', location is LC2_B16, type is buried.
-- synthesized logic cell
_LC2_B16 = LCELL( _EQ003);
_EQ003 = address0 & _LC4_B16;
-- Node name is '~5963~3'
-- Equation name is '~5963~3', location is LC5_B15, type is buried.
-- synthesized logic cell
_LC5_B15 = LCELL( _EQ004);
_EQ004 = address1 & _LC2_B16;
-- Node name is '~5963~4'
-- Equation name is '~5963~4', location is LC6_B15, type is buried.
-- synthesized logic cell
_LC6_B15 = LCELL( _EQ005);
_EQ005 = !address1 & !address2 & address3 & _LC2_B16;
-- Node name is ':5983'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ006);
_EQ006 = address1 & address2 & address3 & !_LC1_B16;
-- Node name is '~6063~1'
-- Equation name is '~6063~1', location is LC1_B13, type is buried.
-- synthesized logic cell
_LC1_B13 = LCELL( _EQ007);
_EQ007 = !address5 & !address6 & !address7;
-- Node name is ':6103'
-- Equation name is '_LC8_B18', type is buried
!_LC8_B18 = _LC8_B18~NOT;
_LC8_B18~NOT = LCELL( _EQ008);
_EQ008 = address2
# address1
# !address3
# _LC1_B16;
-- Node name is '~6106~1'
-- Equation name is '~6106~1', location is LC6_B23, type is buried.
-- synthesized logic cell
!_LC6_B23 = _LC6_B23~NOT;
_LC6_B23~NOT = LCELL( _EQ009);
_EQ009 = !_LC2_B15 & !_LC8_B18;
-- Node name is ':6123'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = LCELL( _EQ010);
_EQ010 = address2 & !address3 & _LC5_B15;
-- Node name is ':6143'
-- Equation name is '_LC2_B18', type is buried
!_LC2_B18 = _LC2_B18~NOT;
_LC2_B18~NOT = LCELL( _EQ011);
_EQ011 = _LC1_B16
# !address1
# address3
# !address2;
-- Node name is ':6148'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ012);
_EQ012 = !_LC3_B23 & _LC8_B18
# _LC2_B15 & !_LC3_B23
# !_LC3_B23 & _LC4_B23;
-- Node name is '~6163~1'
-- Equation name is '~6163~1', location is LC4_B15, type is buried.
-- synthesized logic cell
_LC4_B15 = LCELL( _EQ013);
_EQ013 = !address1 & address2 & _LC2_B16;
-- Node name is '~6183~1'
-- Equation name is '~6183~1', location is LC1_B16, type is buried.
-- synthesized logic cell
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL( _EQ014);
_EQ014 = !address0 & _LC4_B16;
-- Node name is '~6183~2'
-- Equation name is '~6183~2', location is LC6_B18, type is buried.
-- synthesized logic cell
_LC6_B18 = LCELL( _EQ015);
_EQ015 = !address2
# address1
# _LC1_B16;
-- Node name is '~6203~1'
-- Equation name is '~6203~1', location is LC7_B15, type is buried.
-- synthesized logic cell
_LC7_B15 = LCELL( _EQ016);
_EQ016 = !address2 & _LC5_B15;
-- Node name is ':6203'
-- Equation name is '_LC3_B15', type is buried
!_LC3_B15 = _LC3_B15~NOT;
_LC3_B15~NOT = LCELL( _EQ017);
_EQ017 = !_LC5_B15
# address2
# address3;
-- Node name is ':6208'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ018);
_EQ018 = _LC3_B20 & _LC6_B18
# !_LC5_B23 & _LC6_B18
# address3 & _LC3_B20
# address3 & !_LC5_B23;
-- Node name is '~6223~1'
-- Equation name is '~6223~1', location is LC3_B18, type is buried.
-- synthesized logic cell
!_LC3_B18 = _LC3_B18~NOT;
_LC3_B18~NOT = LCELL( _EQ019);
_EQ019 = address1 & !address2 & !_LC1_B16;
-- Node name is ':6223'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ020);
_EQ020 = !address3 & !_LC3_B18;
-- Node name is ':6243'
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = LCELL( _EQ021);
_EQ021 = _LC2_B16 & _LC4_B18;
-- Node name is ':6248'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = LCELL( _EQ022);
_EQ022 = _LC3_B18 & _LC5_B16
# _LC3_B15 & _LC3_B18
# address3 & _LC5_B16
# address3 & _LC3_B15;
-- Node name is '~6263~1'
-- Equation name is '~6263~1', location is LC4_B18, type is buried.
-- synthesized logic cell
_LC4_B18 = LCELL( _EQ023);
_EQ023 = !address1 & !address2 & !address3;
-- Node name is '~6266~1'
-- Equation name is '~6266~1', location is LC7_B16, type is buried.
-- synthesized logic cell
_LC7_B16 = LCELL( _EQ024);
_EQ024 = !address0 & _LC4_B16 & _LC4_B18
# _LC2_B16 & _LC4_B18;
-- Node name is '~6338~1'
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