mux2.vhd

用vhdl写的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX2 IS
PORT(
WR,LED_B:IN STD_LOGIC;
X:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
W1,W2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MUX2;
ARCHITECTURE A OF MUX2 IS
SIGNAL OT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
OT<=X;
PROCESS(WR,LED_B,OT)
BEGIN
  IF(WR='0' AND LED_B='0') THEN W2<=OT;
  ELSE
      W1<=OT;
END IF;
END PROCESS;
END A;