mux3.vhd

来自「用vhdl写的」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX3 IS
PORT(
  sw_b,cs: in std_logic;
  in1,in2,in3: in std_logic_vector(7 downto 0);
  W: OUT std_logic_vector(7 downto 0)
 );
END mux3;

ARCHITECTURE A OF MUX3 IS
 BEGIN
    process(sw_b,cs)
    BEGIN
     if (sw_b='0') then   --in2
       w<=in2;
     elsif (cs='0' ) then --in3
       w<=in3;
	 else
       w<=in1;
    end if;
    END process;
 END A;