counter.vhd

来自「用vhdl写的」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--
ENTITY counter IS
PORT(
  Q, CLR: in std_logic;
  T1,T2,T3,T4: OUT std_logic
 );
END counter;

ARCHITECTURE A OF counter IS
signal X:std_logic_vector(1 downto 0);
 BEGIN
    process(q,clr)
    BEGIN
     if (clr='0') then
        t1<='0';
        t2<='0';
        t3<='0';
        t4<='0';
        x<="00";
     elsif (q'event and q='1') then
        x<=x+1;
 		t1<=(not x(1)) and (not x(0));
		t2<=(not x(1)) and x(0);
        t3<=x(1) and (not x(0));
        t4<=x(1) and x(0);
     end if;
    END process;
 END A;