📄 mux4.rpt
字号:
| | | | | | | | that feed LAB 'D'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
Pin
18 -> * * * * * * * * | - - - * | <-- A
19 -> * * * * * * * * | - - - * | <-- B
36 -> * * * * * * * * | - - - * | <-- C
40 -> * * * * * * * * | - - - * | <-- D
42 -> * - - - - - - - | - - - * | <-- X10
55 -> - * - - - - - - | - - - * | <-- X11
47 -> - - * - - - - - | - - - * | <-- X12
49 -> - - - * - - - - | - - - * | <-- X13
44 -> - - - - * - - - | - - - * | <-- X14
23 -> - - - - - * - - | - - - * | <-- X15
24 -> - - - - - - * - | - - - * | <-- X16
4 -> - - - - - - - * | - - - * | <-- X17
5 -> * - - - - - - - | - - - * | <-- X20
7 -> - * - - - - - - | - - - * | <-- X21
8 -> - - * - - - - - | - - - * | <-- X22
9 -> - - - * - - - - | - - - * | <-- X23
10 -> - - - - * - - - | - - - * | <-- X24
12 -> - - - - - * - - | - - - * | <-- X25
13 -> - - - - - - * - | - - - * | <-- X26
14 -> - - - - - - - * | - - - * | <-- X27
15 -> * - - - - - - - | - - - * | <-- X30
17 -> - * - - - - - - | - - - * | <-- X31
32 -> - - * - - - - - | - - - * | <-- X32
30 -> - - - * - - - - | - - - * | <-- X33
33 -> - - - - * - - - | - - - * | <-- X34
59 -> - - - - - * - - | - - - * | <-- X35
46 -> - - - - - - * - | - - - * | <-- X36
45 -> - - - - - - - * | - - - * | <-- X37
37 -> * - - - - - - - | - - - * | <-- X40
20 -> - * - - - - - - | - - - * | <-- X41
22 -> - - * - - - - - | - - - * | <-- X42
25 -> - - - * - - - - | - - - * | <-- X43
27 -> - - - - * - - - | - - - * | <-- X44
28 -> - - - - - * - - | - - - * | <-- X45
29 -> - - - - - - * - | - - - * | <-- X46
41 -> - - - - - - - * | - - - * | <-- X47
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
** EQUATIONS **
A : INPUT;
B : INPUT;
C : INPUT;
D : INPUT;
X10 : INPUT;
X11 : INPUT;
X12 : INPUT;
X13 : INPUT;
X14 : INPUT;
X15 : INPUT;
X16 : INPUT;
X17 : INPUT;
X20 : INPUT;
X21 : INPUT;
X22 : INPUT;
X23 : INPUT;
X24 : INPUT;
X25 : INPUT;
X26 : INPUT;
X27 : INPUT;
X30 : INPUT;
X31 : INPUT;
X32 : INPUT;
X33 : INPUT;
X34 : INPUT;
X35 : INPUT;
X36 : INPUT;
X37 : INPUT;
X40 : INPUT;
X41 : INPUT;
X42 : INPUT;
X43 : INPUT;
X44 : INPUT;
X45 : INPUT;
X46 : INPUT;
X47 : INPUT;
-- Node name is 'W0'
-- Equation name is 'W0', location is LC051, type is output.
W0 = LCELL( _EQ001 $ GND);
_EQ001 = A & !B & C & D & X20
# A & B & !C & D & X30
# !A & B & C & D & X10
# A & B & C & !D & X40;
-- Node name is 'W1'
-- Equation name is 'W1', location is LC060, type is output.
W1 = LCELL( _EQ002 $ GND);
_EQ002 = A & !B & C & D & X21
# A & B & !C & D & X31
# !A & B & C & D & X11
# A & B & C & !D & X41;
-- Node name is 'W2'
-- Equation name is 'W2', location is LC061, type is output.
W2 = LCELL( _EQ003 $ GND);
_EQ003 = A & !B & C & D & X22
# A & B & !C & D & X32
# !A & B & C & D & X12
# A & B & C & !D & X42;
-- Node name is 'W3'
-- Equation name is 'W3', location is LC049, type is output.
W3 = LCELL( _EQ004 $ GND);
_EQ004 = A & !B & C & D & X23
# A & B & !C & D & X33
# !A & B & C & D & X13
# A & B & C & !D & X43;
-- Node name is 'W4'
-- Equation name is 'W4', location is LC052, type is output.
W4 = LCELL( _EQ005 $ GND);
_EQ005 = A & !B & C & D & X24
# A & B & !C & D & X34
# !A & B & C & D & X14
# A & B & C & !D & X44;
-- Node name is 'W5'
-- Equation name is 'W5', location is LC054, type is output.
W5 = LCELL( _EQ006 $ GND);
_EQ006 = A & !B & C & D & X25
# A & B & !C & D & X35
# !A & B & C & D & X15
# A & B & C & !D & X45;
-- Node name is 'W6'
-- Equation name is 'W6', location is LC056, type is output.
W6 = LCELL( _EQ007 $ GND);
_EQ007 = A & !B & C & D & X26
# A & B & !C & D & X36
# !A & B & C & D & X16
# A & B & C & !D & X46;
-- Node name is 'W7'
-- Equation name is 'W7', location is LC059, type is output.
W7 = LCELL( _EQ008 $ GND);
_EQ008 = A & !B & C & D & X27
# A & B & !C & D & X37
# !A & B & C & D & X17
# A & B & C & !D & X47;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\xiaoning\mux4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,916K
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