📄 mux4.rpt
字号:
Project Information d:\xiaoning\mux4.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/03/2004 19:53:31
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MUX4
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mux4 EPM7064LC68-7 36 8 0 8 0 12 %
User Pins: 36 8 0
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
***** Logic for device 'mux4' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
** ERROR SUMMARY **
Info: Chip 'mux4' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R
E E
V S S
C E E V
C R R C
X X X G X X I G G G G G V V C
2 2 2 N 2 1 N N N N N N E E I W W
3 2 1 D 0 7 T D D D D D D D O 2 1
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
X24 | 10 60 | W7
VCCIO | 11 59 | X35
X25 | 12 58 | GND
X26 | 13 57 | W6
X27 | 14 56 | W5
X30 | 15 55 | X11
GND | 16 54 | W4
X31 | 17 53 | VCCIO
A | 18 EPM7064LC68-7 52 | W0
B | 19 51 | W3
X41 | 20 50 | RESERVED
VCCIO | 21 49 | X13
X42 | 22 48 | GND
X15 | 23 47 | X12
X16 | 24 46 | X36
X43 | 25 45 | X37
GND | 26 44 | X14
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
X X X X V X X G V C X G R D X X V
4 4 4 3 C 3 3 N C 4 N E 4 1 C
4 5 6 3 C 2 4 D C 0 D S 7 0 C
I I E I
O N R O
T V
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 10/12( 83%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 8/16( 50%) 10/12( 83%) 0/16( 0%) 36/36(100%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 44/48 ( 91%)
Total logic cells used: 8/64 ( 12%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 8/64 ( 12%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 8.00
Total fan-in: 64
Total input pins required: 36
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 32
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
18 (1) (A) INPUT 0 0 0 0 0 8 0 A
19 (32) (B) INPUT 0 0 0 0 0 8 0 B
36 (33) (C) INPUT 0 0 0 0 0 8 0 C
40 (37) (C) INPUT 0 0 0 0 0 8 0 D
42 (40) (C) INPUT 0 0 0 0 0 1 0 X10
55 (53) (D) INPUT 0 0 0 0 0 1 0 X11
47 (45) (C) INPUT 0 0 0 0 0 1 0 X12
49 (46) (C) INPUT 0 0 0 0 0 1 0 X13
44 (41) (C) INPUT 0 0 0 0 0 1 0 X14
23 (28) (B) INPUT 0 0 0 0 0 1 0 X15
24 (27) (B) INPUT 0 0 0 0 0 1 0 X16
4 (16) (A) INPUT 0 0 0 0 0 1 0 X17
5 (14) (A) INPUT 0 0 0 0 0 1 0 X20
7 (13) (A) INPUT 0 0 0 0 0 1 0 X21
8 (12) (A) INPUT 0 0 0 0 0 1 0 X22
9 (11) (A) INPUT 0 0 0 0 0 1 0 X23
10 (9) (A) INPUT 0 0 0 0 0 1 0 X24
12 (8) (A) INPUT 0 0 0 0 0 1 0 X25
13 (6) (A) INPUT 0 0 0 0 0 1 0 X26
14 (5) (A) INPUT 0 0 0 0 0 1 0 X27
15 (4) (A) INPUT 0 0 0 0 0 1 0 X30
17 (3) (A) INPUT 0 0 0 0 0 1 0 X31
32 (19) (B) INPUT 0 0 0 0 0 1 0 X32
30 (20) (B) INPUT 0 0 0 0 0 1 0 X33
33 (17) (B) INPUT 0 0 0 0 0 1 0 X34
59 (57) (D) INPUT 0 0 0 0 0 1 0 X35
46 (44) (C) INPUT 0 0 0 0 0 1 0 X36
45 (43) (C) INPUT 0 0 0 0 0 1 0 X37
37 (35) (C) INPUT 0 0 0 0 0 1 0 X40
20 (30) (B) INPUT 0 0 0 0 0 1 0 X41
22 (29) (B) INPUT 0 0 0 0 0 1 0 X42
25 (25) (B) INPUT 0 0 0 0 0 1 0 X43
27 (24) (B) INPUT 0 0 0 0 0 1 0 X44
28 (22) (B) INPUT 0 0 0 0 0 1 0 X45
29 (21) (B) INPUT 0 0 0 0 0 1 0 X46
41 (38) (C) INPUT 0 0 0 0 0 1 0 X47
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
52 51 D OUTPUT t 0 0 0 8 0 0 0 W0
61 60 D OUTPUT t 0 0 0 8 0 0 0 W1
62 61 D OUTPUT t 0 0 0 8 0 0 0 W2
51 49 D OUTPUT t 0 0 0 8 0 0 0 W3
54 52 D OUTPUT t 0 0 0 8 0 0 0 W4
56 54 D OUTPUT t 0 0 0 8 0 0 0 W5
57 56 D OUTPUT t 0 0 0 8 0 0 0 W6
60 59 D OUTPUT t 0 0 0 8 0 0 0 W7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux4.rpt
mux4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------- LC51 W0
| +------------- LC60 W1
| | +----------- LC61 W2
| | | +--------- LC49 W3
| | | | +------- LC52 W4
| | | | | +----- LC54 W5
| | | | | | +--- LC56 W6
| | | | | | | +- LC59 W7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -