mode_control.rpt

用vhdl写的

Pin
1    -> - - - - - - - - - - - - - - - - | - - | <-- CLR
16   -> - - - - - - - - * * * - * * * - | - * | <-- DIN0
14   -> - - - - - - - - * * * - * * * - | - * | <-- DIN1
13   -> - - - - - - - - - - - - * * * - | - * | <-- DIN2
12   -> - - - - - - - - - - - - * * * - | - * | <-- DIN3
11   -> * * * * * * - * * * * * * * * * | * * | <-- DIN4
9    -> * * * * * * - * * * * * * * * * | * * | <-- DIN5
8    -> * * * * * * - * * * * * * * * * | * * | <-- DIN6
43   -> * * * * * * - * * * * * * * * * | * * | <-- DIN7
18   -> - * - - - - - * - - - * - - - - | - * | <-- FC
19   -> - * - - - - - * - - - * - - - - | - * | <-- FZ
17   -> - - * * * * * * * * * - - - - * | - * | <-- Q
4    -> * - - * - * - * * * * - - - - - | * * | <-- T1
20   -> - * - - - - * - - - - - - - - - | - * | <-- T2
2    -> - - * * - - - * * * * - * * * * | * * | <-- T3
44   -> * * - - * - - * * * * * * * * - | * * | <-- T4
LC1  -> * * * * * * * * * * * * * * * * | * * | <-- M


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                      d:\xiaoning\mode_control.rpt
mode_control

** EQUATIONS **

CLR      : INPUT;
DIN0     : INPUT;
DIN1     : INPUT;
DIN2     : INPUT;
DIN3     : INPUT;
DIN4     : INPUT;
DIN5     : INPUT;
DIN6     : INPUT;
DIN7     : INPUT;
FC       : INPUT;
FZ       : INPUT;
Q        : INPUT;
T1       : INPUT;
T2       : INPUT;
T3       : INPUT;
T4       : INPUT;

-- Node name is 'ALU_B' 
-- Equation name is 'ALU_B', location is LC027, type is output.
 ALU_B   = LCELL( _EQ001 $  VCC);
  _EQ001 =  DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4
         # !DIN4 & !DIN5 &  DIN6 &  DIN7 &  M &  T1;

-- Node name is 'CS' 
-- Equation name is 'CS', location is LC025, type is output.
 CS      = LCELL( _EQ002 $ !T2);
  _EQ002 =  DIN4 & !DIN6 &  DIN7 &  FC & !FZ & !M & !T2 &  T4
         # !DIN4 &  DIN5 &  DIN6 &  DIN7 & !M & !T2 &  T4
         #  DIN4 & !DIN5 & !DIN6 &  DIN7 & !M & !T2 &  T4
         #  M &  T2;

-- Node name is 'LDAC' 
-- Equation name is 'LDAC', location is LC023, type is output.
 LDAC    = LCELL( _EQ003 $  GND);
  _EQ003 = !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M & !Q &  T3
         # !DIN5 &  DIN6 &  DIN7 & !M & !Q &  T3;

-- Node name is 'LDAR' 
-- Equation name is 'LDAR', location is LC030, type is output.
 LDAR    = LCELL( _EQ004 $  GND);
  _EQ004 = !DIN4 &  DIN5 &  DIN6 &  DIN7 & !M & !Q &  T3
         #  DIN4 & !DIN6 &  DIN7 & !M & !Q &  T3
         # !M & !Q &  T1;

-- Node name is 'LDDR' 
-- Equation name is 'LDDR', location is LC032, type is output.
 LDDR    = LCELL( _EQ005 $  GND);
  _EQ005 = !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M & !Q &  T4
         # !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M & !Q &  T4;

-- Node name is 'LDFR' 
-- Equation name is 'LDFR', location is LC029, type is output.
 LDFR    = LCELL( _EQ006 $  GND);
  _EQ006 = !DIN4 &  DIN5 & !DIN6 &  DIN7 &  M & !Q &  T1;

-- Node name is 'LDIR' 
-- Equation name is 'LDIR', location is LC031, type is output.
 LDIR    = LCELL( _EQ007 $  GND);
  _EQ007 = !M & !Q &  T2;

-- Node name is 'LDPC' 
-- Equation name is 'LDPC', location is LC024, type is output.
 LDPC    = LCELL( _EQ008 $  GND);
  _EQ008 =  DIN4 &  DIN5 & !DIN6 &  DIN7 &  FC & !FZ & !M & !Q &  T4
         # !DIN4 &  DIN5 &  DIN6 &  DIN7 & !M & !Q &  T3
         # !DIN4 &  DIN5 &  DIN6 &  DIN7 & !M & !Q &  T4
         #  DIN4 & !DIN6 &  DIN7 & !M & !Q &  T3
         # !M & !Q &  T1;

-- Node name is 'LDR0' 
-- Equation name is 'LDR0', location is LC028, type is output.
 LDR0    = LCELL( _EQ009 $  GND);
  _EQ009 = !DIN0 & !DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 &  M & !Q &  T1
         # !DIN0 & !DIN1 & !DIN4 & !DIN5 & !DIN6 &  DIN7 & !M & !Q &  T3
         # !DIN0 & !DIN1 &  DIN4 & !DIN5 &  DIN7 & !M & !Q &  T4;

-- Node name is 'LDR1' 
-- Equation name is 'LDR1', location is LC026, type is output.
 LDR1    = LCELL( _EQ010 $  GND);
  _EQ010 =  DIN0 & !DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 &  M & !Q &  T1
         #  DIN0 & !DIN1 & !DIN4 & !DIN5 & !DIN6 &  DIN7 & !M & !Q &  T3
         #  DIN0 & !DIN1 &  DIN4 & !DIN5 &  DIN7 & !M & !Q &  T4;

-- Node name is 'LDR2' 
-- Equation name is 'LDR2', location is LC017, type is output.
 LDR2    = LCELL( _EQ011 $  GND);
  _EQ011 = !DIN0 &  DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 &  M & !Q &  T1
         # !DIN0 &  DIN1 & !DIN4 & !DIN5 & !DIN6 &  DIN7 & !M & !Q &  T3
         # !DIN0 &  DIN1 &  DIN4 & !DIN5 &  DIN7 & !M & !Q &  T4;

-- Node name is 'LED_B' 
-- Equation name is 'LED_B', location is LC016, type is output.
 LED_B   = LCELL( _EQ012 $  VCC);
  _EQ012 =  DIN4 &  DIN5 &  DIN6 &  DIN7 & !M &  T3;

-- Node name is 'load' 
-- Equation name is 'load', location is LC018, type is output.
 load    = LCELL( _EQ013 $  VCC);
  _EQ013 =  DIN4 &  DIN5 & !DIN6 &  DIN7 &  FC & !FZ & !M &  T4
         # !DIN4 &  DIN5 &  DIN6 &  DIN7 & !M &  T4;

-- Node name is ':37' = 'M' 
-- Equation name is 'M', location is LC001, type is buried.
M        = DFFE( _EQ014 $ !DIN7, !T4, GLOBAL( CLR),  VCC,  VCC);
  _EQ014 = !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M
         # !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M
         # !DIN7 & !M;

-- Node name is 'R0_B' 
-- Equation name is 'R0_B', location is LC020, type is output.
 R0_B    = LCELL( _EQ015 $  _EQ016);
  _EQ015 = !DIN2 & !DIN3 &  DIN4 &  DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X001 & 
              _X002
         # !DIN0 & !DIN1 &  DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X001 & 
              _X002
         # !DIN2 & !DIN3 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X001 & 
              _X002
         # !DIN2 & !DIN3 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T3 &  _X001 & 
              _X002;
  _X001  = EXP(!DIN0 & !DIN1 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T4);
  _X002  = EXP(!DIN0 & !DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4);
  _EQ016 =  _X001 &  _X002;
  _X001  = EXP(!DIN0 & !DIN1 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T4);
  _X002  = EXP(!DIN0 & !DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4);

-- Node name is 'R1_B' 
-- Equation name is 'R1_B', location is LC021, type is output.
 R1_B    = LCELL( _EQ017 $  _EQ018);
  _EQ017 =  DIN2 & !DIN3 &  DIN4 &  DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X003 & 
              _X004
         #  DIN0 & !DIN1 &  DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X003 & 
              _X004
         #  DIN2 & !DIN3 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X003 & 
              _X004
         #  DIN2 & !DIN3 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T3 &  _X003 & 
              _X004;
  _X003  = EXP( DIN0 & !DIN1 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T4);
  _X004  = EXP( DIN0 & !DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4);
  _EQ018 =  _X003 &  _X004;
  _X003  = EXP( DIN0 & !DIN1 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T4);
  _X004  = EXP( DIN0 & !DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4);

-- Node name is 'R2_B' 
-- Equation name is 'R2_B', location is LC022, type is output.
 R2_B    = LCELL( _EQ019 $  _EQ020);
  _EQ019 = !DIN2 &  DIN3 &  DIN4 &  DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X005 & 
              _X006
         # !DIN0 &  DIN1 &  DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X005 & 
              _X006
         # !DIN2 &  DIN3 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T3 &  _X005 & 
              _X006
         # !DIN2 &  DIN3 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T3 &  _X005 & 
              _X006;
  _X005  = EXP(!DIN0 &  DIN1 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T4);
  _X006  = EXP(!DIN0 &  DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4);
  _EQ020 =  _X005 &  _X006;
  _X005  = EXP(!DIN0 &  DIN1 & !DIN4 &  DIN5 & !DIN6 &  DIN7 & !M &  T4);
  _X006  = EXP(!DIN0 &  DIN1 & !DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4);

-- Node name is 'SW_B' 
-- Equation name is 'SW_B', location is LC002, type is output.
 SW_B    = LCELL( _EQ021 $  VCC);
  _EQ021 = !DIN4 & !DIN5 & !DIN6 &  DIN7 & !M &  T3;

-- Node name is 'S0' 
-- Equation name is 'S0', location is LC003, type is output.
 S0      = LCELL( _EQ022 $  GND);
  _EQ022 = !DIN4 &  DIN5 & !DIN6 &  DIN7 &  M &  T1;

-- Node name is 'S1' 
-- Equation name is 'S1', location is LC004, type is output.
 S1      = LCELL( _EQ023 $  GND);
  _EQ023 =  DIN4 & !DIN5 &  DIN6 &  DIN7 & !M &  T4;

-- Node name is 'WR' 
-- Equation name is 'WR', location is LC019, type is output.
 WR      = LCELL( _EQ024 $  VCC);
  _EQ024 =  DIN4 &  DIN5 &  DIN6 &  DIN7 & !M & !Q &  T3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                               d:\xiaoning\mode_control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,428K