📄 mode_control.rpt
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Project Information d:\xiaoning\mode_control.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/03/2004 19:08:20
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MODE_CONTROL
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mode_control
EPM7032LC44-6 16 20 0 21 6 65 %
User Pins: 16 20 0
Project Information d:\xiaoning\mode_control.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLR' chosen for auto global Clear
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
***** Logic for device 'mode_control' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** ERROR SUMMARY **
Info: Chip 'mode_control' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
S D L l
W V C I G D o
S _ T C T L T N N R a
0 B 1 C 3 R 4 7 D 2 d
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
S1 | 7 39 | WR
DIN6 | 8 38 | R0_B
DIN5 | 9 37 | R1_B
GND | 10 36 | R2_B
DIN4 | 11 35 | VCC
DIN3 | 12 EPM7032LC44-6 34 | LDAC
DIN2 | 13 33 | LDPC
DIN1 | 14 32 | CS
VCC | 15 31 | LDR1
DIN0 | 16 30 | GND
Q | 17 29 | ALU_B
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
F F T L G V L L L L L
C Z 2 E N C D D D D D
D D C D I A F R
_ R R R R 0
B
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 16/16(100%) 1/16( 6%) 8/36( 22%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 11/16( 68%) 16/36( 44%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 21/32 ( 65%)
Total shareable expanders used: 6/32 ( 18%)
Total Turbo logic cells used: 21/32 ( 65%)
Total shareable expanders not available (n/a): 6/32 ( 18%)
Average fan-in: 8.14
Total fan-in: 171
Total input pins required: 16
Total output pins required: 20
Total bidirectional pins required: 0
Total logic cells required: 21
Total flipflops required: 1
Total product terms required: 63
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 6
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
1 - - INPUT G 0 0 0 0 0 0 0 CLR
16 (11) (A) INPUT 0 0 0 0 0 6 0 DIN0
14 (10) (A) INPUT 0 0 0 0 0 6 0 DIN1
13 (9) (A) INPUT 0 0 0 0 0 3 0 DIN2
12 (8) (A) INPUT 0 0 0 0 0 3 0 DIN3
11 (7) (A) INPUT 0 0 0 0 0 19 1 DIN4
9 (6) (A) INPUT 0 0 0 0 0 19 1 DIN5
8 (5) (A) INPUT 0 0 0 0 0 19 1 DIN6
43 - - INPUT 0 0 0 0 0 19 1 DIN7
18 (13) (A) INPUT 0 0 0 0 0 3 0 FC
19 (14) (A) INPUT 0 0 0 0 0 3 0 FZ
17 (12) (A) INPUT 0 0 0 0 0 10 0 Q
4 (1) (A) INPUT 0 0 0 0 0 8 0 T1
20 (15) (A) INPUT 0 0 0 0 0 2 0 T2
2 - - INPUT 0 0 0 0 0 12 0 T3
44 - - INPUT 0 0 0 0 0 12 1 T4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
29 27 B OUTPUT t 0 0 0 6 1 0 0 ALU_B
32 25 B OUTPUT t 1 0 1 8 1 0 0 CS
34 23 B OUTPUT t 0 0 0 6 1 0 0 LDAC
26 30 B OUTPUT t 0 0 0 7 1 0 0 LDAR
24 32 B OUTPUT t 0 0 0 6 1 0 0 LDDR
27 29 B OUTPUT t 0 0 0 6 1 0 0 LDFR
25 31 B OUTPUT t 0 0 0 2 1 0 0 LDIR
33 24 B OUTPUT t 1 0 1 10 1 0 0 LDPC
28 28 B OUTPUT t 0 0 0 10 1 0 0 LDR0
31 26 B OUTPUT t 0 0 0 10 1 0 0 LDR1
41 17 B OUTPUT t 0 0 0 10 1 0 0 LDR2
21 16 A OUTPUT t 0 0 0 5 1 0 0 LED_B
40 18 B OUTPUT t 0 0 0 7 1 0 0 load
38 20 B OUTPUT t 3 0 1 10 1 0 0 R0_B
37 21 B OUTPUT t 3 0 1 10 1 0 0 R1_B
36 22 B OUTPUT t 3 0 1 10 1 0 0 R2_B
5 2 A OUTPUT t 0 0 0 5 1 0 0 SW_B
6 3 A OUTPUT t 0 0 0 5 1 0 0 S0
7 4 A OUTPUT t 0 0 0 5 1 0 0 S1
39 19 B OUTPUT t 0 0 0 6 1 0 0 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(4) 1 A DFFE t 1 0 1 5 1 20 1 M (:37)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC16 LED_B
| +------- LC2 SW_B
| | +----- LC3 S0
| | | +--- LC4 S1
| | | | +- LC1 M
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> * * * * * | * * | <-- M
Pin
1 -> - - - - - | - - | <-- CLR
11 -> * * * * * | * * | <-- DIN4
9 -> * * * * * | * * | <-- DIN5
8 -> * * * * * | * * | <-- DIN6
43 -> * * * * * | * * | <-- DIN7
4 -> - - * - - | * * | <-- T1
2 -> * * - - - | * * | <-- T3
44 -> - - - * * | * * | <-- T4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\xiaoning\mode_control.rpt
mode_control
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC27 ALU_B
| +----------------------------- LC25 CS
| | +--------------------------- LC23 LDAC
| | | +------------------------- LC30 LDAR
| | | | +----------------------- LC32 LDDR
| | | | | +--------------------- LC29 LDFR
| | | | | | +------------------- LC31 LDIR
| | | | | | | +----------------- LC24 LDPC
| | | | | | | | +--------------- LC28 LDR0
| | | | | | | | | +------------- LC26 LDR1
| | | | | | | | | | +----------- LC17 LDR2
| | | | | | | | | | | +--------- LC18 load
| | | | | | | | | | | | +------- LC20 R0_B
| | | | | | | | | | | | | +----- LC21 R1_B
| | | | | | | | | | | | | | +--- LC22 R2_B
| | | | | | | | | | | | | | | +- LC19 WR
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
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