rom.rpt
来自「系统实验」· RPT 代码 · 共 844 行 · 第 1/3 页
RPT
844 行
- 6 - C 06 OR2 ! 2 1 0 3 :5779
- 5 - C 10 OR2 0 4 0 2 :5784
- 1 - B 05 AND2 s 4 0 0 7 ~5799~1
- 3 - C 04 AND2 2 1 0 3 :5799
- 2 - C 07 AND2 s ! 2 1 0 4 ~5819~1
- 8 - C 06 OR2 ! 2 1 0 5 :5819
- 4 - C 07 AND2 s 2 1 0 5 ~5839~1
- 4 - C 06 OR2 ! 2 1 0 5 :5839
- 6 - C 01 OR2 0 4 0 1 :5842
- 4 - C 04 AND2 2 1 0 3 :5859
- 6 - C 04 AND2 2 1 0 3 :5879
- 3 - C 06 OR2 ! 2 1 0 3 :5899
- 8 - C 04 OR2 0 4 0 1 :5902
- 7 - C 07 OR2 2 2 0 2 :5971
- 8 - C 01 OR2 0 4 0 1 :5989
- 8 - C 10 OR2 0 4 0 1 :6039
- 2 - C 10 OR2 0 4 0 1 :6048
- 7 - C 04 OR2 0 4 0 1 :6052
- 5 - C 01 OR2 0 3 0 1 :6085
- 3 - C 10 OR2 0 4 0 1 :6136
- 5 - C 02 OR2 0 4 0 1 :6199
- 4 - C 02 OR2 s 0 3 0 1 ~6201~1
- 4 - C 10 AND2 s 0 2 0 4 ~6201~2
- 7 - C 06 OR2 2 2 0 2 :6231
- 6 - C 07 OR2 s 2 2 0 5 ~6232~1
- 7 - C 10 OR2 0 3 0 1 :6240
- 6 - C 10 OR2 0 4 0 1 :6244
- 1 - C 02 OR2 0 4 0 1 :6256
- 1 - C 04 OR2 1 1 1 0 :6279
- 3 - C 01 OR2 1 2 1 0 :6285
- 6 - C 02 AND2 s 0 2 0 1 ~6286~1
- 2 - C 02 AND2 s 0 4 0 2 ~6286~2
- 2 - C 01 AND2 s 0 2 0 3 ~6286~3
- 4 - C 01 OR2 1 2 1 0 :6291
- 5 - C 04 OR2 1 2 1 0 :6297
- 1 - C 01 OR2 1 2 1 0 :6303
- 7 - C 01 OR2 1 2 1 0 :6309
- 8 - C 02 OR2 1 2 1 0 :6315
- 2 - C 04 OR2 s ! 0 2 0 3 ~6316~1
- 3 - C 02 AND2 s 1 1 0 3 ~6316~2
- 7 - C 02 OR2 1 2 1 0 :6321
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\program\vhdl\risc\test\rom.rpt
rom
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
C: 15/ 96( 15%) 21/ 48( 43%) 0/ 48( 0%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\program\vhdl\risc\test\rom.rpt
rom
** EQUATIONS **
address0 : INPUT;
address1 : INPUT;
address2 : INPUT;
address3 : INPUT;
address4 : INPUT;
address5 : INPUT;
address6 : INPUT;
address7 : INPUT;
cs : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC7_C2;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC8_C2;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC7_C1;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC1_C1;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC5_C4;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC4_C1;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC3_C1;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = _LC1_C4;
-- Node name is '~5639~1'
-- Equation name is '~5639~1', location is LC5_C7, type is buried.
-- synthesized logic cell
_LC5_C7 = LCELL( _EQ001);
_EQ001 = address0 & !address1 & _LC1_B5;
-- Node name is ':5639'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = LCELL( _EQ002);
_EQ002 = address0 & !address1 & _LC1_B5 & !_LC5_C6;
-- Node name is '~5659~1'
-- Equation name is '~5659~1', location is LC5_C6, type is buried.
-- synthesized logic cell
!_LC5_C6 = _LC5_C6~NOT;
_LC5_C6~NOT = LCELL( _EQ003);
_EQ003 = address2 & address3;
-- Node name is ':5684'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = LCELL( _EQ004);
_EQ004 = address0 & !address1 & _LC1_B5 & !_LC5_C6
# !address0 & address1 & _LC1_B5 & !_LC5_C6;
-- Node name is '~5739~1'
-- Equation name is '~5739~1', location is LC1_C12, type is buried.
-- synthesized logic cell
_LC1_C12 = LCELL( _EQ005);
_EQ005 = !address2 & address3;
-- Node name is ':5739'
-- Equation name is '_LC2_C6', type is buried
!_LC2_C6 = _LC2_C6~NOT;
_LC2_C6~NOT = LCELL( _EQ006);
_EQ006 = !address3
# address2
# _LC2_C7;
-- Node name is '~5742~1'
-- Equation name is '~5742~1', location is LC1_C10, type is buried.
-- synthesized logic cell
!_LC1_C10 = _LC1_C10~NOT;
_LC1_C10~NOT = LCELL( _EQ007);
_EQ007 = !_LC2_C6 & !_LC6_C7;
-- Node name is ':5759'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = LCELL( _EQ008);
_EQ008 = address2 & !address3 & _LC4_C7;
-- Node name is '~5779~1'
-- Equation name is '~5779~1', location is LC3_C7, type is buried.
-- synthesized logic cell
!_LC3_C7 = _LC3_C7~NOT;
_LC3_C7~NOT = LCELL( _EQ009);
_EQ009 = address0
# !_LC1_B5
# !address1;
-- Node name is ':5779'
-- Equation name is '_LC6_C6', type is buried
!_LC6_C6 = _LC6_C6~NOT;
_LC6_C6~NOT = LCELL( _EQ010);
_EQ010 = !_LC3_C7
# address3
# !address2;
-- Node name is ':5784'
-- Equation name is '_LC5_C10', type is buried
_LC5_C10 = LCELL( _EQ011);
_EQ011 = !_LC1_C6 & _LC2_C6
# !_LC1_C6 & _LC6_C7
# !_LC1_C6 & _LC7_C7;
-- Node name is '~5799~1'
-- Equation name is '~5799~1', location is LC1_B5, type is buried.
-- synthesized logic cell
_LC1_B5 = LCELL( _EQ012);
_EQ012 = !address4 & !address5 & !address6 & !address7;
-- Node name is ':5799'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ013);
_EQ013 = address2 & !address3 & _LC5_C7;
-- Node name is '~5819~1'
-- Equation name is '~5819~1', location is LC2_C7, type is buried.
-- synthesized logic cell
!_LC2_C7 = _LC2_C7~NOT;
_LC2_C7~NOT = LCELL( _EQ014);
_EQ014 = !address0 & !address1 & _LC1_B5;
-- Node name is ':5819'
-- Equation name is '_LC8_C6', type is buried
!_LC8_C6 = _LC8_C6~NOT;
_LC8_C6~NOT = LCELL( _EQ015);
_EQ015 = address3
# !address2
# _LC2_C7;
-- Node name is '~5839~1'
-- Equation name is '~5839~1', location is LC4_C7, type is buried.
-- synthesized logic cell
_LC4_C7 = LCELL( _EQ016);
_EQ016 = address0 & address1 & _LC1_B5;
-- Node name is ':5839'
-- Equation name is '_LC4_C6', type is buried
!_LC4_C6 = _LC4_C6~NOT;
_LC4_C6~NOT = LCELL( _EQ017);
_EQ017 = address3
# address2
# !_LC4_C7;
-- Node name is ':5842'
-- Equation name is '_LC6_C1', type is buried
_LC6_C1 = LCELL( _EQ018);
_EQ018 = _LC5_C10 & !_LC8_C6
# !_LC4_C10 & !_LC8_C6
# _LC4_C6;
-- Node name is ':5859'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = LCELL( _EQ019);
_EQ019 = !address2 & !address3 & _LC3_C7;
-- Node name is ':5879'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ020);
_EQ020 = !address2 & !address3 & _LC5_C7;
-- Node name is ':5899'
-- Equation name is '_LC3_C6', type is buried
!_LC3_C6 = _LC3_C6~NOT;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?