rom.rpt

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_LC3_C6~NOT = LCELL( _EQ021);
  _EQ021 =  address3
         #  address2
         #  _LC2_C7;

-- Node name is ':5902' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ022);
  _EQ022 = !_LC4_C4 &  _LC6_C1
         #  _LC3_C6
         #  _LC6_C4;

-- Node name is ':5971' 
-- Equation name is '_LC7_C7', type is buried 
_LC7_C7  = LCELL( _EQ023);
  _EQ023 =  _LC8_C7
         # !address2 &  address3 &  _LC4_C7;

-- Node name is ':5989' 
-- Equation name is '_LC8_C1', type is buried 
_LC8_C1  = LCELL( _EQ024);
  _EQ024 = !_LC1_C6 & !_LC1_C10 &  _LC7_C7
         # !_LC4_C10;

-- Node name is ':6039' 
-- Equation name is '_LC8_C10', type is buried 
_LC8_C10 = LCELL( _EQ025);
  _EQ025 = !_LC1_C6 &  _LC1_C7 & !_LC2_C6
         # !_LC1_C6 & !_LC2_C6 &  _LC6_C7;

-- Node name is ':6048' 
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ026);
  _EQ026 = !_LC3_C4 & !_LC8_C6 &  _LC8_C10
         # !_LC3_C4 &  _LC6_C6 & !_LC8_C6;

-- Node name is ':6052' 
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = LCELL( _EQ027);
  _EQ027 =  _LC2_C10 & !_LC4_C4
         # !_LC4_C4 &  _LC4_C6
         #  _LC6_C4;

-- Node name is ':6085' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = LCELL( _EQ028);
  _EQ028 =  _LC4_C7 & !_LC5_C6
         #  _LC1_C6;

-- Node name is ':6136' 
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ029);
  _EQ029 =  _LC1_C6
         #  _LC2_C6
         # !_LC6_C7 &  _LC7_C6;

-- Node name is ':6199' 
-- Equation name is '_LC5_C2', type is buried 
_LC5_C2  = LCELL( _EQ030);
  _EQ030 = !_LC1_C6 &  _LC4_C2 &  _LC4_C10
         #  _LC4_C6;

-- Node name is '~6201~1' 
-- Equation name is '~6201~1', location is LC4_C2, type is buried.
-- synthesized logic cell 
_LC4_C2  = LCELL( _EQ031);
  _EQ031 =  _LC1_C7 & !_LC8_C6
         #  _LC2_C6 & !_LC8_C6;

-- Node name is '~6201~2' 
-- Equation name is '~6201~2', location is LC4_C10, type is buried.
-- synthesized logic cell 
_LC4_C10 = LCELL( _EQ032);
  _EQ032 = !_LC3_C4 & !_LC6_C6;

-- Node name is ':6231' 
-- Equation name is '_LC7_C6', type is buried 
_LC7_C6  = LCELL( _EQ033);
  _EQ033 =  address2 &  address3 & !_LC2_C7
         #  address2 &  address3 &  _LC4_C7;

-- Node name is '~6232~1' 
-- Equation name is '~6232~1', location is LC6_C7, type is buried.
-- synthesized logic cell 
_LC6_C7  = LCELL( _EQ034);
  _EQ034 =  address0 & !address1 &  _LC1_B5 &  _LC1_C12
         # !address0 &  address1 &  _LC1_B5 &  _LC1_C12;

-- Node name is ':6240' 
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = LCELL( _EQ035);
  _EQ035 = !_LC2_C6 &  _LC6_C7
         # !_LC2_C6 &  _LC7_C6;

-- Node name is ':6244' 
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = LCELL( _EQ036);
  _EQ036 =  _LC3_C4
         #  _LC1_C6 & !_LC6_C6
         # !_LC6_C6 &  _LC7_C10;

-- Node name is ':6256' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ037);
  _EQ037 = !_LC2_C4
         # !_LC4_C6 &  _LC6_C10 & !_LC8_C6;

-- Node name is ':6279' 
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = LCELL( _EQ038);
  _EQ038 =  cs &  _LC1_C4
         # !cs &  _LC8_C4;

-- Node name is ':6285' 
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = LCELL( _EQ039);
  _EQ039 =  cs &  _LC3_C1
         #  _LC2_C1 &  _LC5_C10;

-- Node name is '~6286~1' 
-- Equation name is '~6286~1', location is LC6_C2, type is buried.
-- synthesized logic cell 
_LC6_C2  = LCELL( _EQ040);
  _EQ040 =  _LC2_C4 &  _LC3_C2;

-- Node name is '~6286~2' 
-- Equation name is '~6286~2', location is LC2_C2, type is buried.
-- synthesized logic cell 
_LC2_C2  = LCELL( _EQ041);
  _EQ041 =  _LC2_C4 &  _LC3_C2 & !_LC4_C6 & !_LC8_C6;

-- Node name is '~6286~3' 
-- Equation name is '~6286~3', location is LC2_C1, type is buried.
-- synthesized logic cell 
_LC2_C1  = LCELL( _EQ042);
  _EQ042 =  _LC2_C2 &  _LC4_C10;

-- Node name is ':6291' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ043);
  _EQ043 =  cs &  _LC4_C1
         #  _LC2_C2 &  _LC8_C1;

-- Node name is ':6297' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ044);
  _EQ044 =  cs &  _LC5_C4
         # !cs & !_LC3_C6 &  _LC7_C4;

-- Node name is ':6303' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = LCELL( _EQ045);
  _EQ045 =  cs &  _LC1_C1
         #  _LC2_C1 &  _LC5_C1;

-- Node name is ':6309' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ046);
  _EQ046 =  cs &  _LC7_C1
         #  _LC2_C1 &  _LC3_C10;

-- Node name is ':6315' 
-- Equation name is '_LC8_C2', type is buried 
_LC8_C2  = LCELL( _EQ047);
  _EQ047 =  cs &  _LC8_C2
         #  _LC5_C2 &  _LC6_C2;

-- Node name is '~6316~1' 
-- Equation name is '~6316~1', location is LC2_C4, type is buried.
-- synthesized logic cell 
!_LC2_C4 = _LC2_C4~NOT;
_LC2_C4~NOT = LCELL( _EQ048);
  _EQ048 =  _LC4_C4
         #  _LC6_C4;

-- Node name is '~6316~2' 
-- Equation name is '~6316~2', location is LC3_C2, type is buried.
-- synthesized logic cell 
_LC3_C2  = LCELL( _EQ049);
  _EQ049 = !cs & !_LC3_C6;

-- Node name is ':6321' 
-- Equation name is '_LC7_C2', type is buried 
_LC7_C2  = LCELL( _EQ050);
  _EQ050 =  cs &  _LC7_C2
         #  _LC1_C2 &  _LC3_C2;



Project Information                          f:\program\vhdl\risc\test\rom.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,634K