pn_correlation.v

verilog fifo

module pn_correlation (reset, clk, data_ch, pn_acq, pn_fnd, wr_data);
    input clk, reset, pn_acq;
    input  data_ch;
    output 	pn_fnd;
    reg 	pn_fnd;
    output [7:0] wr_data;
    
    reg [7:0] 	 sr_data;
    reg [7:0] result;
    integer    i, j, agree, disagree, correlation;
    
    parameter [7:0] K = 8'b10001101;

    assign 	    wr_data = sr_data;
    // Serial to parrallel converter
    always @ (posedge clk or posedge reset)
      if (reset)
	sr_data <= 0;
      else
	sr_data <= {data_ch, sr_data[7:1]};
    
    // Serial to parrallel converter
    // pn_rake
    always @ (posedge clk or posedge reset)
    begin: pn_rake
	if (reset)
	  pn_fnd <= 0;
	else
	begin
	    pn_fnd <= 0;
	    if (pn_acq)
	    begin
		for (j = 0; j <= 7; j = j + 1)
		  if (K[j])
		    result[j] = K[j] & sr_data[j];
		  else
		    result[j] = ~K[j] & ~sr_data[j];
		
		agree = 0;
		disagree = 0;

		for (i = 0; i <= 7; i = i + 1)
		  case (result[i])
		      0: disagree = disagree + 1;
		      1: agree = agree + 1;
		  endcase // case(result[i])
		correlation = agree - disagree;

		if (correlation == 8)
		  pn_fnd <= 1;
		else
		  pn_fnd <= 0;
	    end // if (pn_acq)
	end // else: !if(reset)
    end // block: pn_rake

endmodule // pn_correlation