fifo_2048x8.v

verilog fifo

module fifo_2048x8(rd_clk, wr_clk, wr, rd, reset, wr_addr, rd_addr, wr_data, rd_data);
    input rd_clk, wr_clk, wr, rd, reset;
    input [10:0] wr_addr, rd_addr;
    input [7:0] wr_data;
    output [7:0] rd_data;

// Instantiate the RAM block
//----------------------------------------------------
RAMB16_S9_S9 FIFO_BRAM
	(
	 // write port
	 .WEA(wr),
	 .ENA(1'b1),
	 .SSRA(reset),
	 .CLKA(wr_clk),
	 .ADDRA(wr_addr),
	 .DIA(wr_data),
	 .DIPA(1'b0),
	 //.DOA(),
	 //.DOPA(),

	 // read port
	 .WEB(1'b0),
	 .ENB(rd),
	 .SSRB(reset),
	 .CLKB(rd_clk),
	 .ADDRB(rd_addr),
	 .DIB(8'h00),
	 .DIPB(1'b0),
	 .DOB(rd_data)
	 //.DOPB()
	); 

endmodule // fifo_2048x8