sdr_test.sta.rpt

来自「sdram读写」· RPT 代码 · 共 304 行 · 第 1/5 页

; Fmax       ; Restricted Fmax ; Clock Name                                                               ; Note                                                          ;
+------------+-----------------+--------------------------------------------------------------------------+---------------------------------------------------------------+
; 96.53 MHz  ; 96.53 MHz       ; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 ;                                                               ;
; 125.44 MHz ; 125.44 MHz      ; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1 ;                                                               ;
; 999.0 MHz  ; 340.02 MHz      ; SYS_25MCLK                                                               ; limit due to minimum period restriction (max I/O toggle rate) ;
+------------+-----------------+--------------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------------------------------------------------------------+
; Setup Summary                                                                                        ;
+-----------------------------------------------------------------------------+--------+---------------+
; Clock                                                                       ; Slack  ; End Point TNS ;
+-----------------------------------------------------------------------------+--------+---------------+
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1    ; 2.027  ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0    ; 4.330  ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0 ; 6.662  ; 0.000         ;
; SYS_25MCLK                                                                  ; 38.999 ; 0.000         ;
+-----------------------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------+
; Hold Summary                                                                                        ;
+-----------------------------------------------------------------------------+-------+---------------+
; Clock                                                                       ; Slack ; End Point TNS ;
+-----------------------------------------------------------------------------+-------+---------------+
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0    ; 0.499 ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1    ; 0.499 ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0 ; 0.643 ; 0.000         ;
; SYS_25MCLK                                                                  ; 0.735 ; 0.000         ;
+-----------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------+
; Recovery Summary                                                                                 ;
+--------------------------------------------------------------------------+-------+---------------+
; Clock                                                                    ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------+-------+---------------+
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1 ; 2.742 ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 ; 7.156 ; 0.000         ;
+--------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------+
; Removal Summary                                                                                  ;
+--------------------------------------------------------------------------+-------+---------------+
; Clock                                                                    ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------+-------+---------------+
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 ; 2.578 ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1 ; 2.578 ; 0.000         ;
+--------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------+
; Minimum Pulse Width Summary                                                                       ;
+--------------------------------------------------------------------------+--------+---------------+
; Clock                                                                    ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------+--------+---------------+
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1 ; 1.933  ; 0.000         ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 ; 16.933 ; 0.000         ;
; SYS_25MCLK                                                               ; 18.758 ; 0.000         ;