sdr_test.sta.rpt

sdram读写

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programming logic devices manufactured by Altera and sold by 
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+-----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                     ;
+--------------------+--------------------------------------------------+
; Quartus II Version ; Version 9.1 Build 222 10/21/2009 SJ Full Version ;
; Revision Name      ; sdr_test                                         ;
; Device Family      ; Cyclone II                                       ;
; Device Name        ; EP2C5Q208C8                                      ;
; Timing Models      ; Final                                            ;
; Delay Model        ; Slow Model                                       ;
; Rise/Fall Delays   ; Unavailable                                      ;
+--------------------+--------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; sdr_test.sdc  ; OK     ; Sat Nov 13 16:15:07 2010 ;
+---------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                     ;
+-----------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+--------------------------------------------------------+----------------------------------------------------------+
; Clock Name                                                                  ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master     ; Source                                                 ; Targets                                                  ;
+-----------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+--------------------------------------------------------+----------------------------------------------------------+
; SYS_25MCLK                                                                  ; Base      ; 40.000 ; 25.0 MHz  ; 0.000 ; 20.000 ;            ;           ;             ;       ;        ;           ;            ;          ;            ;                                                        ; { clk }                                                  ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0    ; Generated ; 40.000 ; 25.0 MHz  ; 0.000 ; 20.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; SYS_25MCLK ; uut_sysctrl|uut_PLL_ctrl|altpll_component|pll|inclk[0] ; { uut_sysctrl|uut_PLL_ctrl|altpll_component|pll|clk[0] } ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1    ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000  ; 50.00      ; 1         ; 4           ;       ;        ;           ;            ; false    ; SYS_25MCLK ; uut_sysctrl|uut_PLL_ctrl|altpll_component|pll|inclk[0] ; { uut_sysctrl|uut_PLL_ctrl|altpll_component|pll|clk[1] } ;
; sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0 ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000  ; 50.00      ; 1         ; 4           ;       ;        ;           ;            ; false    ; SYS_25MCLK ; uut_sysctrl|uut_PLL_ctrl|altpll_component|pll|inclk[0] ; { uut_sysctrl|uut_PLL_ctrl|altpll_component|pll|clk[2] } ;
+-----------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------+--------------------------------------------------------+----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fmax Summary                                                                                                                                                            ;
+------------+-----------------+--------------------------------------------------------------------------+---------------------------------------------------------------+