sdr_test.sta.rpt

sdram读写

TimeQuest Timing Analyzer report for sdr_test
Sat Nov 13 16:15:08 2010
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Fmax Summary
  7. Setup Summary
  8. Hold Summary
  9. Recovery Summary
 10. Removal Summary
 11. Minimum Pulse Width Summary
 12. Setup: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1'
 13. Setup: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0'
 14. Setup: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0'
 15. Setup: 'SYS_25MCLK'
 16. Hold: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0'
 17. Hold: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1'
 18. Hold: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0'
 19. Hold: 'SYS_25MCLK'
 20. Recovery: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1'
 21. Recovery: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0'
 22. Removal: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0'
 23. Removal: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1'
 24. Minimum Pulse Width: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1'
 25. Minimum Pulse Width: 'sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0'
 26. Minimum Pulse Width: 'SYS_25MCLK'
 27. Setup Times
 28. Hold Times
 29. Clock to Output Times
 30. Minimum Clock to Output Times
 31. Setup Transfers
 32. Hold Transfers
 33. Recovery Transfers
 34. Removal Transfers
 35. Report TCCS
 36. Report RSKM
 37. Unconstrained Paths
 38. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including,