dcfifo_aal1.tdf

sdram读写

--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="TRUE" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" UNDERFLOW_CHECKING="ON" USE_EAB="ON" data q rdclk rdreq wrclk wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 9.1 cbx_a_gray2bin 2009:10:21:21:22:16:SJ cbx_a_graycounter 2009:10:21:21:22:16:SJ cbx_altdpram 2009:10:21:21:22:16:SJ cbx_altsyncram 2009:10:21:21:22:16:SJ cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_dcfifo 2009:10:21:21:22:16:SJ cbx_fifo_common 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_compare 2009:10:21:21:22:16:SJ cbx_lpm_counter 2009:10:21:21:22:16:SJ cbx_lpm_decode 2009:10:21:21:22:16:SJ cbx_lpm_mux 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_scfifo 2009:10:21:21:22:16:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_stratixiii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ  VERSION_END


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FUNCTION a_gray2bin_kdb (gray[9..0])
RETURNS ( bin[9..0]);
FUNCTION a_graycounter_o96 (aclr, clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION a_graycounter_d2c (clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION a_graycounter_c2c (clock, cnt_en)
RETURNS ( q[9..0]);
FUNCTION altsyncram_3j01 (address_a[8..0], address_b[8..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION dffpipe_c2e (clock, d[0..0])
RETURNS ( q[0..0]);
FUNCTION alt_synch_pipe_fv7 (clock, d[9..0])
RETURNS ( q[9..0]);
FUNCTION dffpipe_909 (clock, d[9..0])
RETURNS ( q[9..0]);
FUNCTION alt_synch_pipe_gv7 (clock, d[9..0])
RETURNS ( q[9..0]);
FUNCTION cmpr_536 (dataa[9..0], datab[9..0])
RETURNS ( aeb);

--synthesis_resources = lut 11 M4K 2 reg 104 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=s102;{-to p0addr} POWER_UP_LEVEL=LOW;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe19|dffe20a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_a09:dffpipe19|dffe20a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe17|dffe18a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_909:dffpipe17|dffe18a* """;

SUBDESIGN dcfifo_aal1
( 
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdreq	:	input;
	wrclk	:	input;
	wrreq	:	input;
	wrusedw[8..0]	:	output;
) 
VARIABLE 
	wrptr_g_gray2bin : a_gray2bin_kdb;
	ws_dgrp_gray2bin : a_gray2bin_kdb;
	rdptr_g1p : a_graycounter_o96;
	wrptr_g1p : a_graycounter_d2c;
	wrptr_gp : a_graycounter_c2c;
	fifo_ram : altsyncram_3j01;
	delayed_wrptr_g[9..0] : dffe;
	p0addr : dffe
		WITH (
			power_up = "low"
		);
	rdptr_g[9..0] : dffe;
	rdaclr : dffpipe_c2e;
	rs_dgwp : alt_synch_pipe_fv7;
	ws_brp : dffpipe_909;
	ws_bwp : dffpipe_909;
	ws_dgrp : alt_synch_pipe_gv7;
	wrusedw_sub_dataa[9..0]	:	WIRE;
	wrusedw_sub_datab[9..0]	:	WIRE;
	wrusedw_sub_result[9..0]	:	WIRE;
	rdempty_eq_comp : cmpr_536;
	wrfull_eq_comp : cmpr_536;
	int_rdempty	: WIRE;
	int_wrfull	: WIRE;
	ram_address_a[8..0]	: WIRE;
	ram_address_b[8..0]	: WIRE;
	rdcnt_addr_ena	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;
	wrptr_gs[9..0]	: WIRE;

BEGIN 
	wrptr_g_gray2bin.gray[9..0] = wrptr_gp.q[9..0];
	ws_dgrp_gray2bin.gray[9..0] = ws_dgrp.q[9..0];
	rdptr_g1p.aclr = (! rdaclr.q[]);
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = rdcnt_addr_ena;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	wrptr_gp.clock = wrclk;
	wrptr_gp.cnt_en = valid_wrreq;
	fifo_ram.address_a[] = ram_address_a[];
	fifo_ram.address_b[] = ram_address_b[];
	fifo_ram.addressstall_b = (! rdcnt_addr_ena);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].clk = wrclk;
	delayed_wrptr_g[].d = wrptr_gp.q[];
	p0addr.clk = rdclk;
	p0addr.clrn = rdaclr.q[];
	p0addr.d = B"1";
	rdptr_g[].clk = rdclk;
	rdptr_g[].d = rdptr_g1p.q[];
	rdptr_g[].ena = valid_rdreq;
	rdaclr.clock = (! rdclk);
	rdaclr.d[] = B"1";
	rs_dgwp.clock = rdclk;
	rs_dgwp.d[] = delayed_wrptr_g[].q;
	ws_brp.clock = wrclk;
	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
	ws_bwp.clock = wrclk;
	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
	ws_dgrp.clock = wrclk;
	ws_dgrp.d[] = rdptr_g[].q;
	wrusedw_sub_result[] = wrusedw_sub_dataa[] - wrusedw_sub_datab[];
	wrusedw_sub_dataa[] = ws_bwp.q[];
	wrusedw_sub_datab[] = ws_brp.q[];
	rdempty_eq_comp.dataa[] = rs_dgwp.q[];
	rdempty_eq_comp.datab[] = rdptr_g[].q;
	wrfull_eq_comp.dataa[] = ws_dgrp.q[];
	wrfull_eq_comp.datab[] = wrptr_gs[];
	int_rdempty = rdempty_eq_comp.aeb;
	int_wrfull = wrfull_eq_comp.aeb;
	q[] = fifo_ram.q_b[];
	ram_address_a[] = ( (wrptr_gp.q[9..9] $ wrptr_gp.q[8..8]), wrptr_gp.q[7..0]);
	ram_address_b[] = ( (rdptr_g1p.q[9..9] $ rdptr_g1p.q[8..8]), rdptr_g1p.q[7..0]);
	rdcnt_addr_ena = (valid_rdreq # (! p0addr.q));
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrptr_gs[] = ( (! wrptr_gp.q[9..9]), (! wrptr_gp.q[8..8]), wrptr_gp.q[7..0]);
	wrusedw[] = ( wrusedw_sub_result[8..0]);
END;
--VALID FILE