prev_cmp_sdr_test.qmsg

sdram读写

{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "13 13 " "Info: 13 registers lost all their fanouts during netlist optimizations. The first 13 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~4 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~5 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~6 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~7 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~5 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~6 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~7 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~8 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~8\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~9 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "723 " "Info: Implemented 723 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Info: Implemented 39 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "633 " "Info: Implemented 633 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/EP2C5/project/sdram_test/sdr_test.map.smsg " "Info: Generated suppressed messages file F:/EP2C5/project/sdram_test/sdr_test.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 13 15:57:18 2010 " "Info: Processing ended: Sat Nov 13 15:57:18 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 13 15:57:20 2010 " "Info: Processing started: Sat Nov 13 15:57:20 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sdr_test -c sdr_test " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sdr_test -c sdr_test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "sdr_test EP2C5Q208C8 " "Info: Selected device EP2C5Q208C8 for design \"sdr_test\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|pll Cyclone II PLL " "Info: Implemented PLL \"sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 907 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1 4 1 0 0 " "Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 904 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0 4 1 0 0 " "Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0 port" {  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 919 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 594 3 0 } }  } 0 0 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208C8 " "Info: Device EP2C8Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 4945 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 4946 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "16 57 " "Critical Warning: No exact pin location assignment(s) for 16 pins of 57 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[0\] " "Info: Pin rdf_dout\[0\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[0] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2164 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[1\] " "Info: Pin rdf_dout\[1\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[1] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2165 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[2\] " "Info: Pin rdf_dout\[2\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[2] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2166 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[3\] " "Info: Pin rdf_dout\[3\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[3] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2167 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[4\] " "Info: Pin rdf_dout\[4\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[4] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2168 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[5\] " "Info: Pin rdf_dout\[5\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[5] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2169 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[6\] " "Info: Pin rdf_dout\[6\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[6] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2170 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[7\] " "Info: Pin rdf_dout\[7\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[7] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorp