prev_cmp_sdr_test.qmsg

sdram读写

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 222 10/21/2009 SJ Full Version " "Info: Version 9.1 Build 222 10/21/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 13 15:57:05 2010 " "Info: Processing started: Sat Nov 13 15:57:05 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sdr_test -c sdr_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sdr_test -c sdr_test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Info: Found entity 1: uart_tx" {  } { { "uart_tx.v" "" { Text "F:/EP2C5/project/sdram_test/uart_tx.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_speed_select.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_speed_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_speed_select " "Info: Found entity 1: uart_speed_select" {  } { { "uart_speed_select.v" "" { Text "F:/EP2C5/project/sdram_test/uart_speed_select.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_ctrl " "Info: Found entity 1: uart_ctrl" {  } { { "uart_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/uart_ctrl.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_test " "Info: Found entity 1: sdr_test" {  } { { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_cmd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_cmd.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_cmd " "Info: Found entity 1: sdram_cmd" {  } { { "sdram_cmd.v" "" { Text "F:/EP2C5/project/sdram_test/sdram_cmd.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_ctrl " "Info: Found entity 1: sdram_ctrl" {  } { { "sdram_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sdram_ctrl.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_top " "Info: Found entity 1: sdram_top" {  } { { "sdram_top.v" "" { Text "F:/EP2C5/project/sdram_test/sdram_top.v" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_wr_data.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdram_wr_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_wr_data " "Info: Found entity 1: sdram_wr_data" {  } { { "sdram_wr_data.v" "" { Text "F:/EP2C5/project/sdram_test/sdram_wr_data.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sys_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sys_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 sys_ctrl " "Info: Found entity 1: sys_ctrl" {  } { { "sys_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sys_ctrl.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pll_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL_ctrl " "Info: Found entity 1: PLL_ctrl" {  } { { "PLL_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/PLL_ctrl.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "wrfifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file wrfifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 wrfifo " "Info: Found entity 1: wrfifo" {  } { { "wrfifo.v" "" { Text "F:/EP2C5/project/sdram_test/wrfifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "sdfifo_ctrl.v(59) " "Warning (10268): Verilog HDL information at sdfifo_ctrl.v(59): always construct contains both blocking and non-blocking assignments" {  } { { "sdfifo_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sdfifo_ctrl.v" 59 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdfifo_ctrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdfifo_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdfifo_ctrl " "Info: Found entity 1: sdfifo_ctrl" {  } { { "sdfifo_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sdfifo_ctrl.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rdfifo.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rdfifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 rdfifo " "Info: Found entity 1: rdfifo" {  } { { "rdfifo.v" "" { Text "F:/EP2C5/project/sdram_test/rdfifo.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}