📄 dcfifo_o2l1.tdf
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--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="TRUE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" UNDERFLOW_CHECKING="ON" USE_EAB="ON" data q rdclk rdreq wrclk wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 9.1 cbx_a_gray2bin 2009:10:21:21:22:16:SJ cbx_a_graycounter 2009:10:21:21:22:16:SJ cbx_altdpram 2009:10:21:21:22:16:SJ cbx_altsyncram 2009:10:21:21:22:16:SJ cbx_cycloneii 2009:10:21:21:22:16:SJ cbx_dcfifo 2009:10:21:21:22:16:SJ cbx_fifo_common 2009:10:21:21:22:16:SJ cbx_lpm_add_sub 2009:10:21:21:22:16:SJ cbx_lpm_compare 2009:10:21:21:22:16:SJ cbx_lpm_counter 2009:10:21:21:22:16:SJ cbx_lpm_decode 2009:10:21:21:22:16:SJ cbx_lpm_mux 2009:10:21:21:22:16:SJ cbx_mgl 2009:10:21:21:37:49:SJ cbx_scfifo 2009:10:21:21:22:16:SJ cbx_stratix 2009:10:21:21:22:16:SJ cbx_stratixii 2009:10:21:21:22:16:SJ cbx_stratixiii 2009:10:21:21:22:16:SJ cbx_util_mgl 2009:10:21:21:22:16:SJ VERSION_END
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION alt_sync_fifo_0oi (aclr, data[15..0], rdclk, rdreq, wrclk, wrreq)
RETURNS ( q[15..0], rdempty, rdusedw[8..0], wrempty, wrfull, wrusedw[8..0]);
--synthesis_resources = lut 102 M4K 2
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=d101";
SUBDESIGN dcfifo_o2l1
(
data[15..0] : input;
q[15..0] : output;
rdclk : input;
rdreq : input;
wrclk : input;
wrreq : input;
wrusedw[8..0] : output;
)
VARIABLE
sync_fifo : alt_sync_fifo_0oi;
aclr : NODE;
BEGIN
sync_fifo.aclr = aclr;
sync_fifo.data[] = data[];
sync_fifo.rdclk = rdclk;
sync_fifo.rdreq = rdreq;
sync_fifo.wrclk = wrclk;
sync_fifo.wrreq = wrreq;
aclr = GND;
q[] = sync_fifo.q[];
wrusedw[] = sync_fifo.wrusedw[];
END;
--VALID FILE
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