sdr_test.hif

sdram读写

-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram
}
# macro_sequence

# end
# entity
altsyncram_e7e1
# storage
db|sdr_test.(17).cnf
db|sdr_test.(17).cnf
# case_insensitive
# source_file
db|altsyncram_e7e1.tdf
5ec4805131e22645a51e835948895ac
7
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
addressstall_a
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram|altsyncram_e7e1:altsyncram14
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram|altsyncram_e7e1:altsyncram14
}
# macro_sequence

# end
# entity
dffpipe_c2e
# storage
db|sdr_test.(18).cnf
db|sdr_test.(18).cnf
# case_insensitive
# source_file
db|dffpipe_c2e.tdf
7a47942b76fd791462b105629c969
7
# used_port {
q0
-1
3
clock
-1
3
d0
-1
2
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_c2e:rdaclr
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_c2e:rdaclr
}
# macro_sequence

# end
# entity
alt_synch_pipe_fv7
# storage
db|sdr_test.(19).cnf
db|sdr_test.(19).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_fv7.tdf
54d264c788e4136184baf69915844
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp
}
# macro_sequence

# end
# entity
dffpipe_909
# storage
db|sdr_test.(20).cnf
db|sdr_test.(20).cnf
# case_insensitive
# source_file
db|dffpipe_909.tdf
1893523a14b781a54673f67d857a5f6
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp|dffpipe_909:dffpipe17
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_brp
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_bwp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp|dffpipe_909:dffpipe17
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_brp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_bwp
}
# macro_sequence

# end
# entity
alt_synch_pipe_gv7
# storage
db|sdr_test.(21).cnf
db|sdr_test.(21).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_gv7.tdf
9b287ad97fc2a432d71eb3167b1a1df
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp
}
# macro_sequence

# end
# entity
dffpipe_a09
# storage
db|sdr_test.(22).cnf
db|sdr_test.(22).cnf
# case_insensitive
# source_file
db|dffpipe_a09.tdf
15478237f840f9af46e0bbb2ce95e9f4
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clock
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_a09:dffpipe19
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_a09:dffpipe19
}
# macro_sequence

# end
# entity
cmpr_536
# storage
db|sdr_test.(23).cnf
db|sdr_test.(23).cnf
# case_insensitive
# source_file
db|cmpr_536.tdf
b8f76b2683c70ddd29382df896a4cc
7
# used_port {
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
aeb
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|cmpr_536:rdempty_eq_comp
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|cmpr_536:wrfull_eq_comp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|cmpr_536:rdempty_eq_comp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|cmpr_536:wrfull_eq_comp
}
# macro_sequence

# end
# entity
rdfifo
# storage
db|sdr_test.(24).cnf
db|sdr_test.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rdfifo.v
4a24d22726a968ebae6ee61d4ea4eedc
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo
}
# macro_sequence

# end
# entity
datagene
# storage
db|sdr_test.(25).cnf
db|sdr_test.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
datagene.v
adcf2f68851bba845e66174d1158f3d8
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
datagene:uut_datagene
}
# macro_sequence

# end
# entity
uart_ctrl
# storage
db|sdr_test.(26).cnf
db|sdr_test.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_ctrl.v
c5bc218b7dcd48dfc4589e73c609a5a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
uart_ctrl:uut_uartctrl
}
# macro_sequence

# end
# entity
uart_tx
# storage
db|sdr_test.(27).cnf
db|sdr_test.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_tx.v
4c5996beb4d5274ebe93c1df496a4b6
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
uart_ctrl:uut_uartctrl|uart_tx:uut_tx
}
# macro_sequence

# end
# entity
uart_speed_select
# storage
db|sdr_test.(28).cnf
db|sdr_test.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_speed_select.v
6062fda6e0f7b8b5bf8de2f9705c37c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
uart_ctrl:uut_uartctrl|uart_speed_select:uut_ss
}
# macro_sequence
BPS_PARA2604	BPS_PARA_21302		
# end
# entity
PLL_ctrl
# storage
db|sdr_test.(2).cnf
db|sdr_test.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
pll_ctrl.v
99e0812142e0d1507952db179af8785e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl
}
# macro_sequence
ALTERA_RESERVED_QISALTERA_RESERVED_QIS
# end
# entity
altpll
# storage
db|sdr_test.(29).cnf
db|sdr_test.(29).cnf
# case_insensitive
# source_file
d:|qii9.1|altera|quartus|libraries|megafunctions|altpll.tdf
34879d2b16c1357da1b2876e4ab5f3
7
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK1
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
40000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_SIGNED_DEC
USR
INVALID_LOCK_MULTIPLIER
5
PARAMETER_SIGNED_DEC
USR
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
4
PARAMETER_SIGNED_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF