sdr_test.hif

sdram读写

PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_UNUSED
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_VCOOVERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_VCOUNDERRANGE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
SCAN_CHAIN_MIF_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
SIM_GATE_LOCK_DEVICE_BEHAVIOR
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
locked
-1
3
inclk
-1
3
extclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
configupdate
-1
1
clkswitch
-1
1
scanclkena
-1
2
pllena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# macro_sequence

# end
# entity
sdram_top
# storage
db|sdr_test.(4).cnf
db|sdr_test.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_top.v
85eabd96b6ca67143ab35f2d85ac5a3
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
sdram_top:uut_sdramtop
}
# macro_sequence

# end
# entity
sdram_ctrl
# storage
db|sdr_test.(5).cnf
db|sdr_test.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_ctrl.v
a0e5d1d21736ef500627ce87ea6365c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
TRP_CLK
000000100
PARAMETER_UNSIGNED_BIN
DEF
TRFC_CLK
000000110
PARAMETER_UNSIGNED_BIN
DEF
TMRD_CLK
000000110
PARAMETER_UNSIGNED_BIN
DEF
TRCD_CLK
000000010
PARAMETER_UNSIGNED_BIN
DEF
TCL_CLK
000000011
PARAMETER_UNSIGNED_BIN
DEF
TREAD_CLK
100000000
PARAMETER_UNSIGNED_BIN
DEF
TWRITE_CLK
100000000
PARAMETER_UNSIGNED_BIN
DEF
TDAL_CLK
000000011
PARAMETER_UNSIGNED_BIN
DEF
}
# include_file {
sdr_para.v
d6e6f5b8fd4bbb2796bc282dbc03e7b
}
# hierarchies {
sdram_top:uut_sdramtop|sdram_ctrl:module_001
}
# macro_sequence
I_NOP5'd0		I_NOP5'd0		I_PRE5'd1		I_NOP5'd0		I_PRE5'd1		I_AR15'd3		I_TRP5'd2		I_TRP5'd2		end_trpcnt_clk_r	== TRP_CLKI_AR15'd3		I_TRP5'd2		I_AR15'd3		I_AR25'd5		I_TRF15'd4		I_TRF15'd4		end_trfccnt_clk_r	== TRFC_CLKI_AR25'd5		I_TRF15'd4		I_AR25'd5		I_AR35'd7		I_TRF25'd6		I_TRF25'd6		end_trfccnt_clk_r	== TRFC_CLKI_AR35'd7		I_TRF25'd6		I_AR35'd7		I_AR45'd9		I_TRF35'd8		I_TRF35'd8		end_trfccnt_clk_r	== TRFC_CLKI_AR45'd9		I_TRF35'd8		I_AR45'd9		I_AR55'd11		I_TRF45'd10		I_TRF45'd10		end_trfccnt_clk_r	== TRFC_CLKI_AR55'd11		I_TRF45'd10		I_AR55'd11		I_AR65'd13		I_TRF55'd12		I_TRF55'd12		end_trfccnt_clk_r	== TRFC_CLKI_AR65'd13		I_TRF55'd12		I_AR65'd13		I_AR75'd15		I_TRF65'd14		I_TRF65'd14		end_trfccnt_clk_r	== TRFC_CLKI_AR75'd15		I_TRF65'd14		I_AR75'd15		I_AR85'd17		I_TRF75'd16		I_TRF75'd16		end_trfccnt_clk_r	== TRFC_CLKI_AR85'd17		I_TRF75'd16		I_AR85'd17		I_MRS5'd19		I_TRF85'd18		I_TRF85'd18		end_trfccnt_clk_r	== TRFC_CLKI_MRS5'd19		I_TRF85'd18		I_MRS5'd19		I_DONE5'd21		I_TMRD5'd20		I_TMRD5'd20		end_tmrdcnt_clk_r	== TMRD_CLKI_DONE5'd21		I_TMRD5'd20		I_DONE5'd21		I_DONE5'd21		I_NOP5'd0		I_DONE5'd21		W_IDLE4'd0		W_IDLE4'd0		W_AR4'd10		W_ACTIVE4'd1		W_IDLE4'd0		W_ACTIVE4'd1		W_READ4'd3		W_WRITE4'd7		W_TRCD4'd2		W_TRCD4'd2		end_trcdcnt_clk_r	== TRCD_CLK-1W_READ4'd3		W_WRITE4'd7		W_TRCD4'd2		W_READ4'd3		W_CL4'd4		W_CL4'd4		end_tclcnt_clk_r       == TCL_CLK-1W_RD4'd5		W_CL4'd4		W_RD4'd5		end_treadcnt_clk_r	== TREAD_CLK+2W_RBST4'd12W_RD4'd5		W_RWAIT4'd6		end_trwaitcnt_clk_r	== TRP_CLKW_IDLE4'd0		W_RWAIT4'd6		W_WRITE4'd7		W_WD4'd8		W_WD4'd8		end_twritecnt_clk_r	== TWRITE_CLK-2W_WBST4'd13W_WD4'd8		W_TDAL4'd9		end_tdalcnt_clk_r	== TDAL_CLK	W_IDLE4'd0		W_TDAL4'd9		W_AR4'd10		W_IDLE4'd0		W_TRFC4'd11		W_TRFC4'd11		end_trfccnt_clk_r	== TRFC_CLKW_IDLE4'd0		W_TRFC4'd11		W_RBST4'd12W_RWAIT4'd6		W_WBST4'd13W_TDAL4'd9		W_IDLE4'd0		W_IDLE4'd0		W_AR4'd10		W_TRCD4'd2		W_WRITE4'd7		W_WD4'd8		W_RD4'd5		W_RD4'd5		end_treadcnt_clk_r	== TREAD_CLK+2I_NOP5'd0		I_PRE5'd1		I_TRP5'd2		end_trpcnt_clk_r	== TRP_CLKI_AR15'd3		I_AR25'd5		I_AR35'd7		I_AR45'd9		I_AR55'd11		I_AR65'd13		I_AR75'd15		I_AR85'd17		I_TRF15'd4		I_TRF25'd6		I_TRF35'd8		I_TRF45'd10		I_TRF55'd12		I_TRF65'd14		I_TRF75'd16		I_TRF85'd18		end_trfccnt_clk_r	== TRFC_CLKI_MRS5'd19		I_TMRD5'd20		end_tmrdcnt_clk_r	== TMRD_CLKI_DONE5'd21		W_IDLE4'd0		W_ACTIVE4'd1		W_TRCD4'd2		end_trcdcnt_clk_r	== TRCD_CLK-1W_CL4'd4		end_tclcnt_clk_r       == TCL_CLK-1W_RD4'd5		end_treadcnt_clk_r	== TREAD_CLK+2W_RWAIT4'd6		end_trwaitcnt_clk_r	== TRP_CLKW_WD4'd8		end_twritecnt_clk_r	== TWRITE_CLK-2W_TDAL4'd9		end_tdalcnt_clk_r	== TDAL_CLK	W_TRFC4'd11		end_trfccnt_clk_r	== TRFC_CLK
# end
# entity
sdram_cmd
# storage
db|sdr_test.(6).cnf
db|sdr_test.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_cmd.v
e774fcaed33d3633454dbb5b24fff2ad
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
sdr_para.v
d6e6f5b8fd4bbb2796bc282dbc03e7b
}
# hierarchies {
sdram_top:uut_sdramtop|sdram_cmd:module_002
}
# macro_sequence
CMD_INIT5'b01111	I_NOP5'd0		I_TRP5'd2		I_TRF15'd4		I_TRF25'd6		I_TRF35'd8		I_TRF45'd10		I_TRF55'd12		I_TRF65'd14		I_TRF75'd16		I_TRF85'd18		I_TMRD5'd20		CMD_NOP5'b10111	I_PRE5'd1		CMD_PRGE5'b10010	I_AR15'd3		I_AR25'd5		I_AR35'd7		I_AR45'd9		I_AR55'd11		I_AR65'd13		I_AR75'd15		I_AR85'd17		CMD_A_REF5'b10001	I_MRS5'd19		CMD_LMR5'b10000	I_DONE5'd21		W_IDLE4'd0		W_TRCD4'd2		W_CL4'd4		W_TRFC4'd11		W_RD4'd5		W_WD4'd8		W_TDAL4'd9		CMD_NOP5'b10111	W_ACTIVE4'd1		CMD_ACTIVE5'b10011	W_READ4'd3		CMD_READ5'b10101	W_WRITE4'd7		CMD_WRITE5'b10100	W_AR4'd10		CMD_A_REF5'b10001	W_RBST4'd12CMD_B_STOP5'b10110	W_WBST4'd13CMD_B_STOP5'b10110	CMD_NOP5'b10111	CMD_NOP5'b10111	
# end
# entity
sdram_wr_data
# storage
db|sdr_test.(7).cnf
db|sdr_test.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_wr_data.v
d66b5175a6449668caa15cc4c5ef96
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
sdr_para.v
d6e6f5b8fd4bbb2796bc282dbc03e7b
}
# hierarchies {
sdram_top:uut_sdramtop|sdram_wr_data:module_003
}
# macro_sequence
W_WRITE4'd7		W_WD4'd8		W_WRITE4'd7		W_WD4'd8		W_RD4'd5		
# end
# entity
sdfifo_ctrl
# storage
db|sdr_test.(8).cnf
db|sdr_test.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdfifo_ctrl.v
832674f2856ed810f940835bf9ce299
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl
}
# macro_sequence

# end
# entity
wrfifo
# storage
db|sdr_test.(9).cnf
db|sdr_test.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
wrfifo.v
66173b84a06bf029a0fa9fc07e5f22c5
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo
}
# macro_sequence

# end
# entity
dcfifo
# storage
db|sdr_test.(10).cnf
db|sdr_test.(10).cnf
# case_insensitive
# source_file
d:|qii9.1|altera|quartus|libraries|megafunctions|dcfifo.tdf
ac581f353dd7b3d5982ba2243a8118
7
# user_parameter {
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
9
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
WRSYNC_DELAYPIPE
3
PARAMETER_UNKNOWN
DEF
CLOCKS_ARE_SYNCHRONIZED
TRUE
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
ADD_USEDW_MSB_BIT
OFF
PARAMETER_UNKNOWN
DEF
WRITE_ACLR_SYNCH
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
dcfifo_aal1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrusedw
-1
3
wrreq
-1
3
wrclk
-1
3
rdreq
-1
3
rdclk
-1
3
q
-1
3
data
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component
}
# macro_sequence

# end
# entity
dcfifo_aal1
# storage
db|sdr_test.(11).cnf
db|sdr_test.(11).cnf
# case_insensitive
# source_file
db|dcfifo_aal1.tdf
178168e2c6eeefa68b8585ca26aa3da
7
# used_port {
wrusedw8
-1
3
wrusedw7
-1
3
wrusedw6
-1
3
wrusedw5
-1
3
wrusedw4
-1
3
wrusedw3
-1
3
wrusedw2
-1
3
wrusedw1
-1
3
wrusedw0
-1
3
wrreq
-1
3
wrclk
-1
3
rdreq
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated
}
# macro_sequence

# end
# entity
a_gray2bin_kdb
# storage
db|sdr_test.(12).cnf
db|sdr_test.(12).cnf
# case_insensitive
# source_file
db|a_gray2bin_kdb.tdf
38c950242690b531f4953ac6c115ca5
7
# used_port {
gray9
-1
3
gray8
-1
3
gray7
-1
3
gray6
-1
3
gray5
-1
3
gray4
-1
3
gray3
-1
3
gray2
-1
3
gray1
-1
3
gray0
-1
3
bin9
-1
3
bin8
-1
3
bin7
-1
3
bin6
-1
3
bin5
-1
3
bin4
-1
3
bin3
-1
3
bin2
-1
3
bin1
-1
3
bin0
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_gray2bin_kdb:wrptr_g_gray2bin
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_gray2bin_kdb:ws_dgrp_gray2bin
}
# macro_sequence

# end
# entity
a_graycounter_o96
# storage
db|sdr_test.(13).cnf
db|sdr_test.(13).cnf
# case_insensitive
# source_file
db|a_graycounter_o96.tdf
db9ef7bd710eb1e2eaffbc81f15ce4
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_o96:rdptr_g1p
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_o96:rdptr_g1p
}
# macro_sequence

# end
# entity
a_graycounter_d2c
# storage
db|sdr_test.(14).cnf
db|sdr_test.(14).cnf
# case_insensitive
# source_file
db|a_graycounter_d2c.tdf
2fea926555882b3f53df945129cb0
7
# used_port {
cnt_en
-1
3
clock
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_d2c:wrptr_g1p
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_d2c:wrptr_g1p
}
# macro_sequence

# end
# entity
a_graycounter_c2c
# storage
db|sdr_test.(15).cnf
db|sdr_test.(15).cnf
# case_insensitive
# source_file
db|a_graycounter_c2c.tdf
358bddc9d441b062f478a06953b4c
7
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
}
# hierarchies {
sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_c2c:wrptr_gp
sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_c2c:wrptr_gp
}
# macro_sequence

# end
# entity
altsyncram_3j01
# storage
db|sdr_test.(16).cnf
db|sdr_test.(16).cnf
# case_insensitive
# source_file
db|altsyncram_3j01.tdf
3d492046a327c7afd9595c1b6ec0de29
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2