prev_cmp_sdr_test.map.qmsg

来自「sdram读写」· QMSG 代码 · 共 77 行 · 第 1/4 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_a09 sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|alt_synch_pipe_gv7:ws_dgrp\|dffpipe_a09:dffpipe19 " "Info: Elaborating entity \"dffpipe_a09\" for hierarchy \"sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|alt_synch_pipe_gv7:ws_dgrp\|dffpipe_a09:dffpipe19\"" {  } { { "db/alt_synch_pipe_gv7.tdf" "dffpipe19" { Text "F:/EP2C5/project/sdram_test/db/alt_synch_pipe_gv7.tdf" 33 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_536.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_536.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_536 " "Info: Found entity 1: cmpr_536" {  } { { "db/cmpr_536.tdf" "" { Text "F:/EP2C5/project/sdram_test/db/cmpr_536.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_536 sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|cmpr_536:rdempty_eq_comp " "Info: Elaborating entity \"cmpr_536\" for hierarchy \"sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|cmpr_536:rdempty_eq_comp\"" {  } { { "db/dcfifo_aal1.tdf" "rdempty_eq_comp" { Text "F:/EP2C5/project/sdram_test/db/dcfifo_aal1.tdf" 75 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rdfifo sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo " "Info: Elaborating entity \"rdfifo\" for hierarchy \"sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\"" {  } { { "sdfifo_ctrl.v" "uut_rdfifo" { Text "F:/EP2C5/project/sdram_test/sdfifo_ctrl.v" 101 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datagene datagene:uut_datagene " "Info: Elaborating entity \"datagene\" for hierarchy \"datagene:uut_datagene\"" {  } { { "sdr_test.v" "uut_datagene" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 170 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_ctrl uart_ctrl:uut_uartctrl " "Info: Elaborating entity \"uart_ctrl\" for hierarchy \"uart_ctrl:uut_uartctrl\"" {  } { { "sdr_test.v" "uut_uartctrl" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 183 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_ctrl:uut_uartctrl\|uart_tx:uut_tx " "Info: Elaborating entity \"uart_tx\" for hierarchy \"uart_ctrl:uut_uartctrl\|uart_tx:uut_tx\"" {  } { { "uart_ctrl.v" "uut_tx" { Text "F:/EP2C5/project/sdram_test/uart_ctrl.v" 48 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_speed_select uart_ctrl:uut_uartctrl\|uart_speed_select:uut_ss " "Info: Elaborating entity \"uart_speed_select\" for hierarchy \"uart_ctrl:uut_uartctrl\|uart_speed_select:uut_ss\"" {  } { { "uart_ctrl.v" "uut_ss" { Text "F:/EP2C5/project/sdram_test/uart_ctrl.v" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "Warning: 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 0 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sdram_cmd.v" "" { Text "F:/EP2C5/project/sdram_test/sdram_cmd.v" 70 -1 0 } } { "uart_tx.v" "" { Text "F:/EP2C5/project/sdram_test/uart_tx.v" 66 -1 0 } } { "sys_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sys_ctrl.v" 46 -1 0 } } { "uart_tx.v" "" { Text "F:/EP2C5/project/sdram_test/uart_tx.v" 45 -1 0 } } { "sys_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sys_ctrl.v" 38 -1 0 } } { "db/a_graycounter_o96.tdf" "" { Text "F:/EP2C5/project/sdram_test/db/a_graycounter_o96.tdf" 37 2 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 -1}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "sdram_ldqm GND " "Warning (13410): Pin \"sdram_ldqm\" is stuck at GND" {  } { { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 46 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "sdram_udqm GND " "Warning (13410): Pin \"sdram_udqm\" is stuck at GND" {  } { { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 45 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "13 13 " "Info: 13 registers lost all their fanouts during netlist optimizations. The first 13 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|rdfifo:uut_rdfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_bwp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\] " "Info: Register \"sdfifo_ctrl:uut_sdffifoctrl\|wrfifo:uut_wrfifo\|dcfifo:dcfifo_component\|dcfifo_aal1:auto_generated\|dffpipe_909:ws_brp\|dffe18a\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~4 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~4\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~5 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~6 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~7 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|work_state_r~7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~5 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~5\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~6 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~6\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~7 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~7\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~8 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~8\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~9 " "Info: Register \"sdram_top:uut_sdramtop\|sdram_ctrl:module_001\|init_state_r~9\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "723 " "Info: Implemented 723 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Info: Implemented 39 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "633 " "Info: Implemented 633 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 PLLs" {  } {  } 0 0 "Implemented %1!d! PLLs" 0 0 "" 0 -1}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/EP2C5/project/sdram_test/sdr_test.map.smsg " "Info: Generated suppressed messages file F:/EP2C5/project/sdram_test/sdr_test.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "185 " "Info: Peak virtual memory: 185 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 13 15:57:18 2010 " "Info: Processing ended: Sat Nov 13 15:57:18 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}