prev_cmp_sdr_test.fit.qmsg

sdram读写

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0 (placed in counter C1 of PLL_1) " "Info: Automatically promoted node sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0 (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 594 3 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2090 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 594 3 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2090 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0 (placed in counter C2 of PLL_1) " "Info: Automatically promoted node sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0 (placed in counter C2 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "altpll.tdf" "" { Text "d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf" 594 3 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2090 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_ctrl:uut_sysctrl\|sysrst_nr2  " "Info: Automatically promoted node sys_ctrl:uut_sysctrl\|sysrst_nr2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "sys_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sys_ctrl.v" 65 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_ctrl:uut_sysctrl|sysrst_nr2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2111 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_ctrl:uut_sysctrl\|sysrst_nr0  " "Info: Automatically promoted node sys_ctrl:uut_sysctrl\|sysrst_nr0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "sys_ctrl.v" "" { Text "F:/EP2C5/project/sdram_test/sys_ctrl.v" 54 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { sys_ctrl:uut_sysctrl|sysrst_nr0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2113 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}