prev_cmp_sdr_test.fit.qmsg

sdram读写

{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 4945 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 4946 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "16 57 " "Critical Warning: No exact pin location assignment(s) for 16 pins of 57 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[0\] " "Info: Pin rdf_dout\[0\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[0] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2164 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[1\] " "Info: Pin rdf_dout\[1\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[1] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2165 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[2\] " "Info: Pin rdf_dout\[2\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[2] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2166 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[3\] " "Info: Pin rdf_dout\[3\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[3] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2167 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[4\] " "Info: Pin rdf_dout\[4\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[4] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2168 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[5\] " "Info: Pin rdf_dout\[5\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[5] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2169 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[6\] " "Info: Pin rdf_dout\[6\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[6] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2170 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[7\] " "Info: Pin rdf_dout\[7\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[7] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2171 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[8\] " "Info: Pin rdf_dout\[8\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[8] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2172 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[9\] " "Info: Pin rdf_dout\[9\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[9] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2173 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[10\] " "Info: Pin rdf_dout\[10\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[10] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2174 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[11\] " "Info: Pin rdf_dout\[11\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[11] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2175 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[12\] " "Info: Pin rdf_dout\[12\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[12] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2176 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[13\] " "Info: Pin rdf_dout\[13\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[13] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2177 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[14\] " "Info: Pin rdf_dout\[14\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[14] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2178 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rdf_dout\[15\] " "Info: Pin rdf_dout\[15\] not assigned to an exact location on the device" {  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { rdf_dout[15] } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 61 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdf_dout[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2179 3016 4146 0}  }  } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1}  } {  } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Timing-driven compilation is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Info: Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_aal1 " "Info: Entity dcfifo_aal1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_a09:dffpipe19\|dffe20a*  " "Info: set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_a09:dffpipe19\|dffe20a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_909:dffpipe17\|dffe18a*  " "Info: set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_909:dffpipe17\|dffe18a* " {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Entity %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1}
{ "Info" "ISTA_SDC_FOUND" "sdr_test.sdc " "Info: Reading SDC File: 'sdr_test.sdc'" {  } {  } 0 0 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL Clocks " "Info: Deriving PLL Clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|inclk\[0\]\} -duty_cycle 50.00 -name \{sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0\} \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|clk\[0\]\} " "Info: create_generated_clock -source \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|inclk\[0\]\} -duty_cycle 50.00 -name \{sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0\} \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|clk\[0\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1\} \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|clk\[1\]\} " "Info: create_generated_clock -source \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1\} \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|clk\[1\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0\} \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|clk\[2\]\} " "Info: create_generated_clock -source \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0\} \{uut_sysctrl\|uut_PLL_ctrl\|altpll_component\|pll\|clk\[2\]\}" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 4 clocks " "Info: Found 4 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "Info:   Period   Clock Name" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "Info: ======== ============" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000   SYS_25MCLK " "Info:   40.000   SYS_25MCLK" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  40.000 sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0 " "Info:   40.000 sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk0" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  10.000 sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1 " "Info:   10.000 sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_clk1" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  10.000 sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0 " "Info:   10.000 sys_ctrl:uut_sysctrl\|PLL_ctrl:uut_PLL_ctrl\|altpll:altpll_component\|_extclk0" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%1!s!" 0 0 "" 0 -1}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G0 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1}  } { { "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/qii9.1/altera/quartus/bin/pin_planner.ppl" { clk } } } { "d:/qii9.1/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/qii9.1/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "sdr_test.v" "" { Text "F:/EP2C5/project/sdram_test/sdr_test.v" 27 -1 0 } } { "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/qii9.1/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/EP2C5/project/sdram_test/" 0 { } { { 0 { 0 ""} 0 2272 3016 4146 0}  }  } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}