sdr_test.sdc

来自「sdram读写」· SDC 代码 · 共 214 行 · 第 1/2 页

set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[10]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[11]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[11]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[2]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[2]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[3]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[3]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[4]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[4]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[5]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[5]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[6]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[6]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[7]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[7]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[8]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[8]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_addr[9]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_addr[9]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_ba[0]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_ba[0]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_ba[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_ba[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_cas_n}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_cas_n}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_cke}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_cke}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_cs_n}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_cs_n}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[0]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[0]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[10]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[10]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[11]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[11]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[12]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[12]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[13]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[13]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[14]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[14]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[15]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[15]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[1]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[1]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[2]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[2]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[3]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[3]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[4]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[4]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[5]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[5]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[6]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[6]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[7]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[7]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[8]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[8]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_data[9]}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_data[9]}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_ras_n}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_ras_n}]
set_output_delay -add_delay -max -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  1.500 [get_ports {sdram_we_n}]
set_output_delay -add_delay -min -clock [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -0.750 [get_ports {sdram_we_n}]


#**************************************************************
# Set Clock Groups
#**************************************************************



#**************************************************************
# Set False Path
#**************************************************************

set_false_path -from [get_ports {sdram_cke rst_n}] 


#**************************************************************
# Set Multicycle Path
#**************************************************************

set_multicycle_path -setup -end -from  [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1}]  -to  [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}] 2
set_multicycle_path -setup -end -from  [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_extclk0}]  -to  [get_clocks {sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component|_clk1}] 2


#**************************************************************
# Set Maximum Delay
#**************************************************************



#**************************************************************
# Set Minimum Delay
#**************************************************************



#**************************************************************
# Set Input Transition
#**************************************************************