sdr_test.map.rpt

sdram读写

; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                         ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                          ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------+
; uart_tx.v                        ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/uart_tx.v                       ;
; uart_speed_select.v              ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/uart_speed_select.v             ;
; uart_ctrl.v                      ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/uart_ctrl.v                     ;
; sdr_test.v                       ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sdr_test.v                      ;
; sdram_cmd.v                      ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sdram_cmd.v                     ;
; sdram_ctrl.v                     ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sdram_ctrl.v                    ;
; sdram_top.v                      ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sdram_top.v                     ;
; sdram_wr_data.v                  ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sdram_wr_data.v                 ;
; sys_ctrl.v                       ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sys_ctrl.v                      ;
; PLL_ctrl.v                       ; yes             ; User Wizard-Generated File   ; F:/EP2C5/project/sdram_test/PLL_ctrl.v                      ;
; wrfifo.v                         ; yes             ; User Wizard-Generated File   ; F:/EP2C5/project/sdram_test/wrfifo.v                        ;
; sdfifo_ctrl.v                    ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/sdfifo_ctrl.v                   ;
; rdfifo.v                         ; yes             ; User Wizard-Generated File   ; F:/EP2C5/project/sdram_test/rdfifo.v                        ;
; datagene.v                       ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/datagene.v                      ;
; led_test.v                       ; yes             ; User Verilog HDL File        ; F:/EP2C5/project/sdram_test/led_test.v                      ;
; sdr_para.v                       ; yes             ; Auto-Found Verilog HDL File  ; F:/EP2C5/project/sdram_test/sdr_para.v                      ;
; altpll.tdf                       ; yes             ; Megafunction                 ; d:/qii9.1/altera/quartus/libraries/megafunctions/altpll.tdf ;
; dcfifo.tdf                       ; yes             ; Megafunction                 ; d:/qii9.1/altera/quartus/libraries/megafunctions/dcfifo.tdf ;
; db/dcfifo_aal1.tdf               ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/dcfifo_aal1.tdf              ;
; db/a_gray2bin_kdb.tdf            ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/a_gray2bin_kdb.tdf           ;
; db/a_graycounter_o96.tdf         ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/a_graycounter_o96.tdf        ;
; db/a_graycounter_d2c.tdf         ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/a_graycounter_d2c.tdf        ;
; db/a_graycounter_c2c.tdf         ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/a_graycounter_c2c.tdf        ;
; db/altsyncram_3j01.tdf           ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/altsyncram_3j01.tdf          ;
; db/altsyncram_e7e1.tdf           ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/altsyncram_e7e1.tdf          ;
; db/dffpipe_c2e.tdf               ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/dffpipe_c2e.tdf              ;
; db/alt_synch_pipe_fv7.tdf        ; yes             ; Auto-Generated Megafunction  ; F:/EP2C5/project/sdram_test/db/alt_synch_pipe_fv7.tdf       ;