📄 sdr_test.map.rpt
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Analysis & Synthesis report for sdr_test
Sat Nov 13 16:14:42 2010
Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. State Machine - |sdr_test|sdram_top:uut_sdramtop|sdram_ctrl:module_001|work_state_r
10. State Machine - |sdr_test|sdram_top:uut_sdramtop|sdram_ctrl:module_001|init_state_r
11. Registers Protected by Synthesis
12. Registers Removed During Synthesis
13. General Register Statistics
14. Inverted Register Statistics
15. Multiplexer Restructuring Statistics (Restructuring Performed)
16. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component
17. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated
18. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_o96:rdptr_g1p
19. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_d2c:wrptr_g1p
20. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_c2c:wrptr_gp
21. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram
22. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram|altsyncram_e7e1:altsyncram14
23. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_c2e:rdaclr
24. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp
25. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp|dffpipe_909:dffpipe17
26. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_brp
27. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_bwp
28. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp
29. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_a09:dffpipe19
30. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component
31. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated
32. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_o96:rdptr_g1p
33. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_d2c:wrptr_g1p
34. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|a_graycounter_c2c:wrptr_gp
35. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram
36. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|altsyncram_3j01:fifo_ram|altsyncram_e7e1:altsyncram14
37. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_c2e:rdaclr
38. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp
39. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_fv7:rs_dgwp|dffpipe_909:dffpipe17
40. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_brp
41. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|dffpipe_909:ws_bwp
42. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp
43. Source assignments for sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component|dcfifo_aal1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_a09:dffpipe19
44. Parameter Settings for User Entity Instance: sys_ctrl:uut_sysctrl|PLL_ctrl:uut_PLL_ctrl|altpll:altpll_component
45. Parameter Settings for User Entity Instance: sdram_top:uut_sdramtop|sdram_ctrl:module_001
46. Parameter Settings for User Entity Instance: sdfifo_ctrl:uut_sdffifoctrl|wrfifo:uut_wrfifo|dcfifo:dcfifo_component
47. Parameter Settings for User Entity Instance: sdfifo_ctrl:uut_sdffifoctrl|rdfifo:uut_rdfifo|dcfifo:dcfifo_component
48. altpll Parameter Settings by Entity Instance
49. dcfifo Parameter Settings by Entity Instance
50. Port Connectivity Checks: "sdram_top:uut_sdramtop"
51. Analysis & Synthesis Messages
52. Analysis & Synthesis Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
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