sdr_test.qsf

sdram读写

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		sdr_test_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY sdr_test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:34:01  MAY 11, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 9.1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_FILE uart_tx.v
set_global_assignment -name VERILOG_FILE uart_speed_select.v
set_global_assignment -name VERILOG_FILE uart_ctrl.v
set_global_assignment -name VERILOG_FILE sdr_test.v
set_global_assignment -name VERILOG_FILE sdram_cmd.v
set_global_assignment -name VERILOG_FILE sdram_ctrl.v
set_global_assignment -name VERILOG_FILE sdram_top.v
set_global_assignment -name VERILOG_FILE sdram_wr_data.v
set_global_assignment -name VERILOG_FILE sys_ctrl.v
set_global_assignment -name QIP_FILE PLL_ctrl.qip
set_global_assignment -name QIP_FILE wrfifo.qip
set_global_assignment -name VERILOG_FILE sdfifo_ctrl.v
set_global_assignment -name QIP_FILE rdfifo.qip
set_global_assignment -name VERILOG_FILE datagene.v
set_global_assignment -name MISC_FILE "E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/sdr_test.dpf"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name MISC_FILE "E:/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/sdr_test.dpf"
set_global_assignment -name MISC_FILE "E:/xjwjj/SF-EP1CV3_ex/verilog_prj/ex14_SDRAM/sdram_mdl/sdr_test.dpf"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name MISC_FILE "F:/ep1c3/verilog_prj/ex14_SDRAM/sdram_mdl/sdr_test.dpf"

set_location_assignment PIN_23 -to clk
set_location_assignment PIN_129 -to clk1
set_location_assignment PIN_31 -to led[0]
set_location_assignment PIN_33 -to led[1]
set_location_assignment PIN_34 -to led[2]
set_location_assignment PIN_35 -to led[3]

set_location_assignment PIN_24 -to rst_n
set_location_assignment PIN_27 -to key[1]
set_location_assignment PIN_28 -to key[2]
set_location_assignment PIN_30 -to key[3]
set_location_assignment PIN_39 -to rs232_rx
set_location_assignment PIN_37 -to rs232_tx

set_location_assignment PIN_90 -to sd_data
set_location_assignment PIN_89 -to sd_clk
set_location_assignment PIN_88 -to sd_cmd
set_location_assignment PIN_87 -to sd_cs

set_location_assignment PIN_94 -to irda_rx
set_location_assignment PIN_92 -to irda_tx

set_location_assignment PIN_58 -to i2c_sda
set_location_assignment PIN_59 -to i2c_scl

set_location_assignment PIN_4 -to flash_data[0]
set_location_assignment PIN_208 -to flash_data[1]
set_location_assignment PIN_206 -to flash_data[2]
set_location_assignment PIN_203 -to flash_data[3]
set_location_assignment PIN_200 -to flash_data[4]
set_location_assignment PIN_198 -to flash_data[5]
set_location_assignment PIN_195 -to flash_data[6]
set_location_assignment PIN_192 -to flash_data[7]
set_location_assignment PIN_3 -to flash_data[8]
set_location_assignment PIN_207 -to flash_data[9]
set_location_assignment PIN_205 -to flash_data[10]
set_location_assignment PIN_201 -to flash_data[11]
set_location_assignment PIN_199 -to flash_data[12]
set_location_assignment PIN_197 -to flash_data[13]
set_location_assignment PIN_193 -to flash_data[14]
set_location_assignment PIN_191 -to flash_data[15]

set_location_assignment PIN_8 -to flash_addr[0]
set_location_assignment PIN_188 -to flash_addr[1]
set_location_assignment PIN_187 -to flash_addr[2]
set_location_assignment PIN_185 -to flash_addr[3]
set_location_assignment PIN_182 -to flash_addr[4]
set_location_assignment PIN_181 -to flash_addr[5]
set_location_assignment PIN_180 -to flash_addr[6]
set_location_assignment PIN_179 -to flash_addr[7]
set_location_assignment PIN_169 -to flash_addr[8]
set_location_assignment PIN_168 -to flash_addr[9]
set_location_assignment PIN_165 -to flash_addr[10]
set_location_assignment PIN_164 -to flash_addr[11]
set_location_assignment PIN_163 -to flash_addr[12]
set_location_assignment PIN_162 -to flash_addr[13]
set_location_assignment PIN_161 -to flash_addr[14]
set_location_assignment PIN_160 -to flash_addr[15]
set_location_assignment PIN_189 -to flash_addr[16]
set_location_assignment PIN_176 -to flash_addr[17]
set_location_assignment PIN_175 -to flash_addr[18]
set_location_assignment PIN_170 -to flash_addr[19]


set_location_assignment PIN_171 -to flash_we
set_location_assignment PIN_173 -to flash_rst
set_location_assignment PIN_6 -to flash_cs
set_location_assignment PIN_5 -to flash_oe

set_location_assignment PIN_95 -to sdram_data[0]
set_location_assignment PIN_96 -to sdram_data[1]
set_location_assignment PIN_97 -to sdram_data[2]
set_location_assignment PIN_99 -to sdram_data[3]
set_location_assignment PIN_101 -to sdram_data[4]
set_location_assignment PIN_102 -to sdram_data[5]
set_location_assignment PIN_103 -to sdram_data[6]
set_location_assignment PIN_104 -to sdram_data[7]
set_location_assignment PIN_114 -to sdram_data[8]
set_location_assignment PIN_113 -to sdram_data[9]
set_location_assignment PIN_112 -to sdram_data[10]
set_location_assignment PIN_110 -to sdram_data[11]
set_location_assignment PIN_108 -to sdram_data[12]
set_location_assignment PIN_107 -to sdram_data[13]
set_location_assignment PIN_106 -to sdram_data[14]
set_location_assignment PIN_105 -to sdram_data[15]

set_location_assignment PIN_149 -to sdram_addr[0]
set_location_assignment PIN_150 -to sdram_addr[1]
set_location_assignment PIN_151 -to sdram_addr[2]
set_location_assignment PIN_152 -to sdram_addr[3]
set_location_assignment PIN_137 -to sdram_addr[4]
set_location_assignment PIN_135 -to sdram_addr[5]
set_location_assignment PIN_134 -to sdram_addr[6]
set_location_assignment PIN_133 -to sdram_addr[7]
set_location_assignment PIN_128 -to sdram_addr[8]
set_location_assignment PIN_127 -to sdram_addr[9]
set_location_assignment PIN_147 -to sdram_addr[10]
set_location_assignment PIN_118 -to sdram_addr[11]

set_location_assignment PIN_117 -to sdram_cke
set_location_assignment PIN_116 -to sdram_clk
set_location_assignment PIN_144 -to sdram_cs_n
set_location_assignment PIN_141 -to sdram_we_n
set_location_assignment PIN_142 -to sdram_cas_n
set_location_assignment PIN_143 -to sdram_ras_n
set_location_assignment PIN_145 -to sdram_ba[0]
set_location_assignment PIN_146 -to sdram_ba[1]
set_location_assignment PIN_139 -to sdram_ldqm
set_location_assignment PIN_115 -to sdram_udqm









set_global_assignment -name MISC_FILE "F:/ep1c3/myprj/sdram_test/sdr_test.dpf"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_gene -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME tb_gene -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut_datagene -section_id tb_gene
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_gene -section_id tb_gene
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/tb_gene.v -section_id tb_gene
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name MISC_FILE "F:/ep1c3/sdram_test/sdr_test.dpf"
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name MISC_FILE "F:/ep1c3/sd_v1/sdram_test/sdr_test.dpf"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name MISC_FILE "F:/EP2C5/project/sdram_test/sdr_test.dpf"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE led_test.v