sdrsd50_071010.v

sdram读写

/*==================================================================
 * Copyright(c) Samsung Electronics Co., 1997,1998. All rights reseved.
 *
 * Verilog Behavioral Model of Synchronous DRAM 
 *
 * Device: -  16M SDRAM(2nd Gen., 3rd Gen., 4th Gen., 5th Gen.) 
 *	   -  64M SDRAM(2nd Gen., 3rd Gen., 4th Gen., 5th Gen.)
 *	   - 128M SDRAM(1st Gen., 2nd Gen.,)
 *	   - 256M SDRAM(2nd Gen.)
 *
 * Description : This is a synchrounous high data rate DRAM, 
 *		 fabricated with SAMSUNG's high performance  
 *               CMOS technology.                                
 *
 * Developer   : Jae-Ha Kim.
 *  		 CAE Team. Semiconductor R&D Centor. 
 *		 Semiconductor Division. Samsung Electronics Co.
 *
 * Revision    : Yong-Cheol Bae. ( e-mail: [e-mail] )
 * 1.0~2.3	 DRAM2 Design. Semiconductor R&D Centor. 
 *		 Semiconductor Division. Samsung Electronics Co.
 * Revision    : Kyung-Woo Nam. ( e-mail: [e-mail] )
 * 3.0~		 DRAM2 Design. Semiconductor R&D Centor. 
 *		 Semiconductor Division. Samsung Electronics Co.
 * Revision    : Yun-Woo Kim. ( e-mail: [e-mail] )
 * 5.0~		 DRAM Design. Semiconductor R&D Centor. 
 *		 Semiconductor Division. Samsung Electronics Co.
 *==================================================================
 * Revision No. : V2.3 
 * date		: Aug. 20. 1997
 *		: Oct. 22. 1997
 *		: Jan. 15. 1998   - 16M 4Gen. & 64M 3Gen. spec update
 *		: Jun. 30. 1998   - 16M 4Gen. & 64M 3Gen. & 2Mx32 & 
 *		                  128M 1Gen. & 256M 2Gen. AC spec update
 *		: Oct. 08. 1998   - all-bank precharge revision
 *		                  bank note change: ba0=MSB,ba1=LSB @ 4banks
 *		: Nov. 18. 1998   - option set for verbose (e.g. +define+v )
 *		                  128M 2Gen. AC spec added. 
 *                                conformed model through verilog-XL 2.6.27 
 * Revision No. : V3.0 
 * date		: Apr. 07. 1999   - tRDL=2
 *			1. parameterize auto-precharge address : ADDR_AP
 *			2. divide auto-precharge process read/write
 *			3. divide precharge_flag_kill process normal/read_autopre/write_autopre
 *			4. generate wr_autoprecharge2 process excuting when tRDL=2
 *			5. modify same-bank-autoprecharge-disable function
 *			   (disable gapless, other bank interrupt case)
 * Revision No. : V3.1 
 * date         : May. 19. 1999  
 *			1. Add 16M 5th Gen. LVTTL(-10,-8,-8.7,-7,-6)
 *			2. Modify 2Mx32 5th Gen. tSAC value
 * Revision No. : V3.2 
 * date         : Jun. 11. 1999  
 *			1. Modify -A AC parameter(64M 5th, 128M 2th, 256M 2th)
 * Revision No. : V3.3 
 * date         : Jun. 24. 1999  
 *			1. After 64MSD3, auto_flagx signal is not used, 
 *			   let auto_flagx be not enabled to device which is after 64MSD3
 *			2. compile new versions 
 *			   verilog-xl : 2.7.17, NC-verilog : 2.1., VCS : 5.0.1a
 * Revision No. : V3.4 
 * date         : Jul. 12. 1999  
 *			1. To prevent roundoff error in AC parameter violation check procedure,
 *			   define MARGIN paramter. (MARGIN=0.1ns now)
 * Revision No. : V3.5 
 * date         : Sep. 28. 1999  
 *			1. Warning message 'tCCmax violation' is appeared during self refresh operation.
 *			   When self refresh or precharge-power down, clk can be don't care state. (can stay 'low' or 'high'-level)
 *                         Therefore tCCmax violation should not be checked during self refresh or prech. power down.
 * Revision No. : V3.6 
 * date         : Dec. 14. 1999  
 *			1. Make MODELSIM version and add partial REF./VREFi change function for NOKIA
 * Revision No. : V3.7 
 * date         : Jul. 11. 2000  
 *			1. Add dynamic memory allocation function using VERILOG-XL PLI,
 *			   then you must build verilog-XL excutable file containing PLI, and use +define+DYMEM option.
 * Revision No. : V3.8 
 * date         : Jul. 13. 2000  
 *			1. Add 128M SDRAM 3rd/4th Gen., 256M SDRAM 3rd Gen.
 * Revision No. : V3.9
 * date         : Feb. 5. 2001
 *                      1. remove CL2 parameter at -A, -7,... when violated, error messages are printed.
 * Revision No. : V4.0
 * date         : Jun. 11. 2001
 *                      1. 128M SDRAM X32 MCP (64M SDRAM X16 7th) parameter added
 * Revision No. : V4.1
 * date         : Jun. 23. 2001
 *                      1. 256M SDRAM 4th parameters are added
 * Revision No. : V4.2
 * date         : Jul. 31. 2001
 *                      1. because array of reg is not work at vcs 6.0, change array of reg to real variable (TRAS_PP, TPRE_P)
 * Revision No. : V4.3
 * date         : Aug. 09. 2001
 *                      1. There is an error that use "<" instead of ">", in tRASmax violation check routine.
 * Revision No. : V4.4
 * date         : Oct. 05. 2001
 *                      1. Add 128M Mobile SDRAM 5th Gen. (8Mx16, D-die)
 *                      2. Add 64M Mobile SDRAM 7th Gen. (2Mx32, F-die)
 * Revision No. : V4.5
 * date         : Nov. 23. 2001
 *                      1. Add mobile function (EMRS:PASR/TCSR/DSC, DPD:pin/cmd control)
 * Revision No. : V5.0
 * date         : Sep. 1. 2006
 *                      1.The section of the wire declaration is added the delay by LIY.
 *==================================================================
 */


`timescale    1ns / 10ps
 
`define K1	1024
`define M1	1048576
`define BYTE	8
//-----------
`define M64		//64M sdram
`define X16		//data port 16bit
`define S60		//60ns access time
`define NBANK4	//4 bank

//-----------    
    
`ifdef M64
/////////////////////////////////////////////////////////////////////////////
	`ifdef S60 //M64
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
        `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M64
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M64

`ifdef M128
/////////////////////////////////////////////////////////////////////////////
	`ifdef S60 //M128
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M128
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M128

`ifdef M256
/////////////////////////////////////////////////////////////////////////////
	`ifdef S60 //M256
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M256
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M256


`ifdef DPD_PIN
module
sdram(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
`else
module
sdram(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi);
`endif
    `ifdef M16
	`define TBITS	16*`M1
	`define nBank	2
        `define ADDRTOP	10
	`define	ADDR_AP	10
    `endif
    `ifdef M64
	`define TBITS		64*`M1
	`define	ADDR_AP	10
    	`ifdef NBANK2
      	    `define nBank	2	
	    `ifdef X32
	    	`define ADDRTOP	11
	    `else
            	`define ADDRTOP	12
	    `endif
    	`endif
        `ifdef NBANK4
     	    `define nBank	4	
	    `ifdef X32
            	`define ADDRTOP	10
	    `else
	    	`define ADDRTOP	11
	    `endif
    	`endif
    `endif
    `ifdef M128
	`define TBITS	128*`M1
	`define nBank	4
        `define ADDRTOP	11
	`define	ADDR_AP	10
    `endif
    `ifdef M256
	`define TBITS	256*`M1
	`define nBank	4
        `define ADDRTOP	12
	`define	ADDR_AP	10
    `endif

`ifdef M16
        `ifdef G2
                `define M16G2_M641G
	`else
                `define M16G3_M64G2
                `define M64G3_M128_M256
        `endif
`endif

`ifdef M64
                `define M64_M128_M256    // for prech_reg 
        `ifdef G1
                `define M16G2_M641G
        `else
        `ifdef G2
                `define M16G3_M64G2
        `else
                `define M16G4_M64G3
                `define M64G3_M128_M256
        `endif
        `endif
`endif

`ifdef M128  // 98.6.30 BYC
                `define M64_M128_M256    // for prech_reg 
		`define M128_M256        // RFU, c_addr 10->11 
                `define M64G3_M128_M256  // from M64G3
                `define M16G4_M64G3
`endif
`ifdef M256  // 98.6.30 BYC
                `define M64_M128_M256    // for prech_reg 
		`define M128_M256        // RFU, c_addr 10->11 
                `define M64G3_M128_M256  // from M64G3
                `define M16G4_M64G3
`endif

`ifdef tCC1
`else
	`define NO_CL1
`endif
`ifdef tSAC1
`else
	`define NO_CL1
`endif
`ifdef tSHZ1
`else
	`define NO_CL1
`endif
`ifdef tCC2
`else
	`define NO_CL2
`endif
`ifdef tSAC2
`else
	`define NO_CL2
`endif
`ifdef tSHZ2
`else
	`define NO_CL2
`endif
`ifdef tCC3
`else
	`define NO_CL3
`endif
`ifdef tSAC3
`else
	`define NO_CL3
`endif
`ifdef tSHZ3
`else
	`define NO_CL3
`endif

`ifdef M128_M256
    `ifdef X4
    	`define M128_M256_X4			// 98.6.30 BYC
    	`define B		4		// number of bit(x4)
    	`define nCOL		11
    	`define PAGEDEPTH	2048
	`define nDQM		1
    `endif
    `ifdef X8
        `define B		8		// number of bit(x8)
    	`define nCOL		10
    	`define PAGEDEPTH	1024
    	`define nDQM		1
    `endif
    `ifdef X16
    	`define B		16		// number of bit(x16)
    	`define nCOL		9
    	`define PAGEDEPTH	512
	`define nDQM		2
    `endif
    `ifdef X32
    	`define B		32		// number of bit(x32)
    	`define nCOL		8
    	`define PAGEDEPTH	256
	`define nDQM		4
    `endif
`else
    `ifdef X4
    	`define B		4		// number of bit(x4)
    	`define nCOL		10
    	`define PAGEDEPTH	1024
	`define nDQM		1
    `endif
    `ifdef X8
        `define B		8		// number of bit(x8)
    	`define nCOL		9
    	`define PAGEDEPTH	512
    	`define nDQM		1
    `endif
    `ifdef X16
    	`define B		16		// number of bit(x16)
    	`define nCOL		8
    	`define PAGEDEPTH	256
	`define nDQM		2
    `endif
    `ifdef X32
    	`define B		32		// number of bit(x32)
    	`define nCOL		8
    	`define PAGEDEPTH	128
	`define nDQM		4
    `endif
`endif

`ifdef	tRDL
`else
	`define	tRDL	1