transcript

sdram读写

#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1462  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 1155
restart
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
add wave sim:/tb_sdrtest/sd/\\uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk1\\
restart
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1462  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# current receive data is   1
# current receive data is   2
# current receive data is   3
# current receive data is   4
# current receive data is   5
# current receive data is   6
# current receive data is   7
# current receive data is   8
# current receive data is   9
# current receive data is  10
# current receive data is  11
# current receive data is  12
# current receive data is  13
# current receive data is  14
# current receive data is  15
# current receive data is  16
# current receive data is  17
# current receive data is  18
# current receive data is  19
# current receive data is  20
# current receive data is  21
# current receive data is  22
# current receive data is  23
# current receive data is  24
# current receive data is  25
# current receive data is  26
# current receive data is  27
# Simulation Successful
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/print_task.v line 62
# Compile of sdr_test.vo was successful.
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1472  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 3164
view signals
# .signals
add wave sim:/tb_sdrtest/sd/\\uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk1\\
restart
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
run -continue
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1472  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# current receive data is   1
# current receive data is   2
# current receive data is   3
# current receive data is   4
add wave sim:/tb_sdrtest/sd/\\uut_sdramtop|module_003|sdr_dout\\
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 2215
restart
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1472  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# current receive data is   1
# current receive data is   2
# current receive data is   3
# current receive data is   4
# current receive data is   5
# Compile of altera_mf.v was successful.
# Compile of cyclone_atoms.v was successful.
# Compile of print_task.v was successful.
# Compile of sdr_test.vo was successful.
# Compile of sys_ctrl_task.v was successful.
# Compile of tb_sdrtest.v was successful.
# 6 compiles, 0 failed with no errors. 
# current receive data is   6
# current receive data is   7
# current receive data is   8
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 6031
# Compile of sdr_test.vo was successful.
run -all
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 5688
add wave sim:/tb_sdrtest/sd/\\uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk1\\
add wave sim:/tb_sdrtest/sd/\\uut_sdramtop|module_003|sdr_dout\\
add wave sim:/tb_sdrtest/sd/\\uut_datagene|addr\\
restart
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sdram_rd_req" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sdram_rd_ack" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sdram_wr_ack" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sys_data_in" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sys_data_out" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sdram_busy" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/sys_dout_rdy" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/rdf_dout" 
# Warning in wave window restart:  No objects found matching "/tb_sdrtest/rdf_rdreq" 
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1462  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# current receive data is   1
# current receive data is   2
# current receive data is   3
# current receive data is   4
# current receive data is   5
# current receive data is   6
# current receive data is   7
# current receive data is   8
# current receive data is   9
# current receive data is  10
# current receive data is  11
# Compile of sdr_test.vo was successful.
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 5688
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
add wave sim:/tb_sdrtest/sd/\\uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk1\\
add wave sim:/tb_sdrtest/sd/\\uut_sdramtop|module_003|sdr_dout\\
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1462  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# current receive data is   1
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 3164