📄 transcript

📁 sdram读写
💻
📖 第 1 页 / 共 3 页
字号:
12 3 下一页
# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl 
#  OpenFile "E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/sdram_test.mpf" 
# Loading project sdram_test
# Compile of altera_mf.v failed with 1 errors.
# Compile of cyclone_atoms.v failed with 1 errors.
# Compile of print_task.v failed with 1 errors.
# Compile of sdr_test.vo failed with 1 errors.
# Compile of sys_ctrl_task.v failed with 1 errors.
# Compile of tb_sdrtest.v failed with 1 errors.
# 6 compiles, 6 failed with 6 errors. 
# Compile of cyclone_atoms.v failed with 1 errors.
# Compile of cyclone_atoms.v failed with 1 errors.
vlib cyclone
vmap cyclone cyclone
# Modifying E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/sdram_test.mpf
# Compile of cyclone_atoms.v was successful.
# Compile of cyclone_atoms.v was successful.
# Compile of altera_mf.v was successful.
# Compile of cyclone_atoms.v was successful.
# Compile of print_task.v was successful.
# Compile of sdr_test.vo was successful.
# Compile of sys_ctrl_task.v was successful.
# Compile of tb_sdrtest.v failed with 1 errors.
# 6 compiles, 1 failed with 1 error. 
# Compile of tb_sdrtest.v failed with 1 errors.
# Compile of tb_sdrtest.v was successful.
# compile Main C:/Modeltech_5.7d/win32/vlog -work {$MODEL_TECH/../verilog} -refresh 
# Model Technology ModelSim SE vlog 5.7d Compiler 2003.05 May 10 2003
# -- Skipping package vl_types
# compile Main C:/Modeltech_5.7d/win32/vcom -work {$MODEL_TECH/../verilog} -refresh 
# Model Technology ModelSim SE vcom 5.7d Compiler 2003.05 May 10 2003
# -- Loading package standard
# -- Compiling package vl_types
# -- Compiling package body vl_types
# -- Loading package vl_types
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1472  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 2215
# Compile of sdr_test.vo was successful.
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1462  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 3164
# Compile of sdr_test.vo was successful.
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 1462  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 6009
# Compile of sdr_test.vo was successful.
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# Loading cyclone.CYCLONE_PRIM_DFFE
run -all
# Loading sdr_test_v.sdo
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd
# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.
# Time: 0  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll .n1
#  Note : Cyclone PLL was reset
# Time: 948  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
#  Note : Cyclone PLL locked to incoming clock
# Time: 663315  Instance: tb_sdrtest.sd.\uut_sysctrl|uut_PLL_ctrl|altpll_component|pll 
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 591
run -all
# Break key hit 
# Break at E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/cyclone_atoms.v line 3164
# Compile of tb_sdrtest.v failed with 1 errors.
# Compile of tb_sdrtest.v was successful.
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# ** Fatal: (vsim-3365) E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/tb_sdrtest.v(77): Too many port connections. Expected 19, found 21.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd File: E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/sdr_test.vo
# FATAL ERROR while loading design
# Error loading design
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# ** Fatal: (vsim-3365) E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/tb_sdrtest.v(77): Too many port connections. Expected 19, found 21.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd File: E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/sdr_test.vo
# FATAL ERROR while loading design
# Error loading design
vsim cyclone.tb_sdrtest
# vsim cyclone.tb_sdrtest 
# Loading cyclone.tb_sdrtest
# Loading cyclone.print_task
# ** Warning: (vsim-3009) [TSCALE] - Module 'print_task' does not have a `timescale directive in effect, but previous modules do.
#         Region: /tb_sdrtest/print
# Loading cyclone.sys_ctrl_task
# Loading cyclone.sdr_test
# Loading cyclone.cyclone_io
# Loading cyclone.cyclone_mux21
# Loading cyclone.cyclone_dffe
# Loading cyclone.cyclone_asynch_io
# Loading cyclone.cyclone_lcell
# Loading cyclone.cyclone_asynch_lcell
# Loading cyclone.cyclone_lcell_register
# Loading cyclone.cyclone_pll
# Loading cyclone.cyclone_m_cntr
# Loading cyclone.cyclone_n_cntr
# Loading cyclone.cyclone_scale_cntr
# Loading cyclone.cyclone_pll_reg
# Loading cyclone.cyclone_ram_block
# Loading cyclone.cyclone_ram_register
# Loading cyclone.cyclone_ram_pulse_generator
# ** Fatal: (vsim-3365) E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/tb_sdrtest.v(77): Too many port connections. Expected 19, found 21.
#    Time: 0 ps  Iteration: 0  Instance: /tb_sdrtest/sd File: E:/Personal/VGA_SD_photos/sdram_verilog/verilog/sdram_mdl/simulation/modelsim/sdr_test.vo
# FATAL ERROR while loading design
# Error loading design
# Compile of sdr_test.vo was successful.
vsim cyclone.tb_sdrtest
12 3 下一页
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -