sdr_test.vo

sdram读写

wire \uut_sdramtop|module_002|sdram_addr_r~10_combout ;
wire \uut_sdramtop|module_002|sdram_addr_r~11_combout ;
wire \uut_datagene|rd_addr[6]~23_combout ;
wire \uut_sdramtop|module_002|Selector21~0_combout ;
wire \uut_sdramtop|module_002|Selector21~1_combout ;
wire \uut_sdramtop|module_002|Selector20~1_combout ;
wire \uut_sdramtop|module_002|Selector19~1_combout ;
wire \uut_sdramtop|module_002|Selector18~0_combout ;
wire \uut_sdramtop|module_002|Selector18~1_combout ;
wire \uut_datagene|rd_addr[10]~31_combout ;
wire \uut_sdramtop|module_002|Selector17~0_combout ;
wire \uut_sdramtop|module_002|Selector17~1_combout ;
wire \uut_sdramtop|module_002|Selector16~0_combout ;
wire \uut_sdramtop|module_002|Selector16~1_combout ;
wire \uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk0 ;
wire \uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk0~clkctrl_outclk ;
wire \uut_uartctrl|uut_tx|num[0]~0_combout ;
wire \uut_sdramtop|module_003|sdr_dout[0]~feeder_combout ;
wire \uut_sdramtop|module_003|Equal2~0_combout ;
wire \uut_sdramtop|module_003|sdr_dout[2]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[3]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[4]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[5]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[7]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[8]~feeder_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~0_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~1_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~2_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~3_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~4_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~5_combout ;
wire \uut_uartctrl|uut_tx|rs232_tx_r~regout ;
wire \uut_led_test|led[0]~0_combout ;
wire \uut_led_test|cnt[1]~24_combout ;
wire \uut_led_test|cnt[1]~25 ;
wire \uut_led_test|cnt[2]~27 ;
wire \uut_led_test|cnt[3]~29 ;
wire \uut_led_test|cnt[4]~30_combout ;
wire \uut_led_test|cnt[4]~31 ;
wire \uut_led_test|cnt[5]~33 ;
wire \uut_led_test|cnt[6]~34_combout ;
wire \uut_led_test|cnt[6]~35 ;
wire \uut_led_test|cnt[7]~37 ;
wire \uut_led_test|cnt[8]~38_combout ;
wire \uut_led_test|cnt[8]~39 ;
wire \uut_led_test|cnt[9]~41 ;
wire \uut_led_test|cnt[10]~42_combout ;
wire \uut_led_test|cnt[10]~43 ;
wire \uut_led_test|cnt[11]~44_combout ;
wire \uut_led_test|cnt[11]~45 ;
wire \uut_led_test|cnt[12]~46_combout ;
wire \uut_led_test|cnt[12]~47 ;
wire \uut_led_test|cnt[13]~48_combout ;
wire \uut_led_test|cnt[13]~49 ;
wire \uut_led_test|cnt[14]~50_combout ;
wire \uut_led_test|cnt[14]~51 ;
wire \uut_led_test|cnt[15]~52_combout ;
wire \uut_led_test|cnt[15]~53 ;
wire \uut_led_test|cnt[16]~55 ;
wire \uut_led_test|cnt[17]~56_combout ;
wire \uut_led_test|cnt[17]~57 ;
wire \uut_led_test|cnt[18]~59 ;
wire \uut_led_test|cnt[19]~61 ;
wire \uut_led_test|cnt[20]~62_combout ;
wire \uut_led_test|cnt[20]~63 ;
wire \uut_led_test|cnt[21]~65 ;
wire \uut_led_test|cnt[22]~66_combout ;
wire \uut_led_test|cnt[22]~67 ;
wire \uut_led_test|cnt[23]~68_combout ;
wire \uut_led_test|Equal0~6_combout ;
wire \uut_led_test|cnt[7]~36_combout ;
wire \uut_led_test|Equal0~1_combout ;
wire \uut_led_test|cnt[9]~40_combout ;
wire \uut_led_test|Equal0~2_combout ;
wire \uut_led_test|cnt[0]~72_combout ;
wire \uut_led_test|cnt[2]~26_combout ;
wire \uut_led_test|Equal0~0_combout ;
wire \uut_led_test|Equal0~4_combout ;
wire \uut_led_test|cnt[23]~69 ;
wire \uut_led_test|cnt[24]~70_combout ;
wire \uut_led_test|Equal0~7_combout ;
wire \uut_led_test|Add1~0_combout ;
wire \uut_led_test|Add1~1_combout ;
wire \uut_led_test|Add1~2_combout ;
wire \uut_sdramtop|module_003|sdr_dout[9]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[10]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[11]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[12]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[13]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[14]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_dout[15]~feeder_combout ;
wire \uut_datagene|LessThan1~1_combout ;
wire \uut_datagene|always6~0_combout ;
wire \uut_datagene|wrf_dinr[0]~15_combout ;
wire \uut_datagene|wrf_dinr[1]~16_combout ;
wire \uut_datagene|wrf_dinr[1]~17 ;
wire \uut_datagene|wrf_dinr[2]~18_combout ;
wire \uut_datagene|wrf_dinr[2]~19 ;
wire \uut_datagene|wrf_dinr[3]~20_combout ;
wire \uut_datagene|wrf_dinr[3]~21 ;
wire \uut_datagene|wrf_dinr[4]~22_combout ;
wire \uut_datagene|wrf_dinr[4]~23 ;
wire \uut_datagene|wrf_dinr[5]~24_combout ;
wire \uut_datagene|wrf_dinr[5]~25 ;
wire \uut_datagene|wrf_dinr[6]~26_combout ;
wire \uut_datagene|wrf_dinr[6]~27 ;
wire \uut_datagene|wrf_dinr[7]~28_combout ;
wire \uut_datagene|wrf_dinr[7]~29 ;
wire \uut_datagene|wrf_dinr[8]~30_combout ;
wire \uut_sdramtop|module_003|sdr_din[0]~feeder_combout ;
wire \uut_sdramtop|module_003|always0~0_combout ;
wire \uut_sdramtop|module_003|sdr_dlink~regout ;
wire \uut_sdramtop|module_003|sdr_din[1]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[3]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[4]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[5]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[6]~feeder_combout ;
wire \uut_datagene|wrf_dinr[8]~31 ;
wire \uut_datagene|wrf_dinr[9]~32_combout ;
wire \uut_datagene|wrf_dinr[9]~33 ;
wire \uut_datagene|wrf_dinr[10]~34_combout ;
wire \uut_datagene|wrf_dinr[10]~35 ;
wire \uut_datagene|wrf_dinr[11]~36_combout ;
wire \uut_datagene|wrf_dinr[11]~37 ;
wire \uut_datagene|wrf_dinr[12]~38_combout ;
wire \uut_datagene|wrf_dinr[12]~39 ;
wire \uut_datagene|wrf_dinr[13]~40_combout ;
wire \uut_datagene|wrf_dinr[13]~41 ;
wire \uut_datagene|wrf_dinr[14]~42_combout ;
wire \uut_datagene|wrf_dinr[14]~43 ;
wire \uut_datagene|wrf_dinr[15]~44_combout ;
wire \uut_sdramtop|module_003|sdr_din[10]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[11]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[12]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[13]~feeder_combout ;
wire \uut_sdramtop|module_003|sdr_din[15]~feeder_combout ;
wire [24:0] \uut_led_test|cnt ;
wire [3:0] \uut_uartctrl|uut_tx|num ;
wire [9:0] \uut_datagene|cntwr ;
wire [13:0] \uut_datagene|rd_addr ;
wire [15:0] \uut_datagene|wrf_dinr ;
wire [0:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|rdempty_eq_comp|aneb_result_wire ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe19|dffe20a ;
wire [0:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|rdaclr|dffe16a ;
wire [15:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|wrptr_gp|counter13a ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|delayed_wrptr_g ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|rdptr_g ;
wire [15:0] \uut_sdramtop|module_003|sdr_din ;
wire [1:0] \uut_sdramtop|module_002|sdram_ba_r ;
wire [10:0] \uut_sdramtop|module_001|cnt_15us ;
wire [8:0] \uut_sdramtop|module_001|cnt_clk_r ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ws_bwp|dffe18a ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ws_brp|dffe18a ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe17|dffe18a ;
wire [15:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrptr_gp|counter13a ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|rdptr_g1p|counter7a ;
wire [8:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ram_address_a ;
wire [8:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ram_address_b ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_bwp|dffe18a ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_brp|dffe18a ;
wire [3:0] \uut_led_test|led ;
wire [12:0] \uut_uartctrl|uut_ss|cnt ;
wire [13:0] \uut_datagene|delay ;
wire [13:0] \uut_datagene|wr_addr ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe17|dffe18a ;
wire [9:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|rdptr_g1p|counter7a ;
wire [8:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ram_address_b ;
wire [15:0] \uut_sdramtop|module_003|sdr_dout ;
wire [11:0] \uut_sdramtop|module_002|sdram_addr_r ;
wire [4:0] \uut_sdramtop|module_002|sdram_cmd_r ;
wire [14:0] \uut_sdramtop|module_001|cnt_200us ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe19|dffe20a ;
wire [0:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|rdaclr|dffe16a ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|delayed_wrptr_g ;
wire [9:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|rdptr_g ;

wire [2:0] \uut_sysctrl|uut_PLL_ctrl|altpll_component|pll_CLK_bus ;
wire [8:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus ;
wire [6:0] \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus ;
wire [8:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus ;
wire [6:0] \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus ;

assign \uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk0  = \uut_sysctrl|uut_PLL_ctrl|altpll_component|pll_CLK_bus [0];
assign \uut_sysctrl|uut_PLL_ctrl|altpll_component|_clk1  = \uut_sysctrl|uut_PLL_ctrl|altpll_component|pll_CLK_bus [1];
assign \uut_sysctrl|uut_PLL_ctrl|altpll_component|_extclk0  = \uut_sysctrl|uut_PLL_ctrl|altpll_component|pll_CLK_bus [2];

assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [0] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [0];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [1] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [1];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [2] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [2];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [3] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [3];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [4] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [4];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [5] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [5];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [6] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [6];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [7] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [7];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [8] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [8];

assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [9] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [0];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [10] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [1];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [11] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [2];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [12] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [3];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [13] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [4];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [14] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [5];
assign \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [15] = \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a9_PORTADATAOUT_bus [6];

assign \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [0] = \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATAOUT_bus [0];
assign \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|q_a [1] = \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|fifo_ram|altsyncram14|ram_block15a0_PORTADATA